An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a lower etch stop layer (ESL); a middle low-k (LK) dielectric layer over the lower ESL; a supporting layer over the middle LK dielectric layer; an upper LK dielectric layer over the supporting layer; an upper conductive feature in the upper LK dielectric layer, wherein the upper conductive feature is through the supporting layer; a gap along an interface of the upper conductive feature and the upper LK dielectric layer; and an upper ESL over the upper LK dielectric layer, the upper conductive feature, and the gap.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method of forming an interconnect structure, comprising: forming a lower etch stop layer (ESL); forming a middle low-k (LK) dielectric layer over the lower ESL; forming a supporting layer over the middle LK dielectric layer; forming an upper LK dielectric layer over the supporting layer; forming an upper conductive feature in the upper LK dielectric layer through the supporting layer; forming a gap along an interface of the upper conductive feature and the upper LK dielectric layer and along an interface of the upper conductive feature and the middle LK dielectric layer, wherein the step of forming the gap along the interface of the upper conductive feature and the upper LK dielectric layer is performed by removing a portion of the upper LK dielectric layer along the interface by a wet etching process; and forming an upper ESL over the upper LK dielectric layer, the upper conductive feature, and the gap.
2. The method of claim 1 , wherein the gap comprises air.
3. The method of claim 1 , wherein the gap extends under a bottom surface of the lower ESL.
4. The method of claim 1 , wherein: forming an upper conductive feature in the upper LK dielectric layer through the supporting layer comprises: etching an opening through the upper LK dielectric layer and the supporting layer, the etching the opening forming a damaged layer along walls of the opening; and filling the opening with a conductive material to form the upper conductive feature; and forming a gap along an interface of the upper conductive feature and the upper LK dielectric layer comprises: removing portions of the damaged layer along the interface of the upper conductive feature and the upper LK dielectric layer.
5. The method of claim 4 , wherein etching the opening through the upper LK dielectric layer and the supporting layer comprises: performing a plasma dry etch process to form the opening.
6. The method of claim 1 , wherein the upper conductive feature comprises a metal line, the metal line extending through the supporting layer.
7. The method of claim 6 , wherein the upper conductive feature further comprises a via in the middle LK dielectric layer, the via being contiguous with the metal line and through the lower ESL.
8. A method comprising: forming a first etch stop layer over a first low-k dielectric layer; forming a second low-k dielectric layer over the first etch stop layer; forming a first dielectric layer over the second low-k dielectric layer; forming a third low-k dielectric layer over the first dielectric layer; etching an opening through the third low-k dielectric layer and the first dielectric layer, the etching the opening forming a damaged layer along walls of the opening; filling the opening with a conductive material to form a first conductive feature, wherein the first conductive feature comprises a metal line and a via contiguous with the metal line, the metal line extending through the first dielectric layer, the via being in the second low-k dielectric layer and extending through the first etch stop layer; removing portions of the damaged layer along an interface of the first conductive feature and the third low-k dielectric layer to form a gap along the interface of the first conductive feature and the third low-k dielectric layer; and forming a second etch stop layer over the third low-k dielectric layer, the first conductive feature, and the gap.
9. The method of claim 8 , wherein the gap extends along an interface of the first conductive feature and the second low-k dielectric layer.
10. The method of claim 8 , wherein the gap is an air gap.
11. The method of claim 8 , wherein etching the opening through the third low-k dielectric layer and the first dielectric layer comprises: performing a plasma dry etch process to form the opening.
12. The method of claim 8 wherein removing portions of the damaged layer comprises: performing a wet etch process to remove portions of the damaged layer.
13. The method of claim 8 , wherein the gap extends under a bottom surface of the first etch stop layer.
14. A method comprising: forming a first dielectric layer over a first low-k dielectric layer; forming a second low-k dielectric layer over the first dielectric layer; performing a plasma dry etch process to form an opening through the second low-k dielectric layer and the first dielectric layer, the plasma dry etch process forming a damaged layer along walls of the opening; filling the opening with a conductive material to form a first conductive feature; performing a wet etch process to remove portions of the damaged layer along an interface of the first conductive feature and the second low-k dielectric layer, wherein the wet etch process forms a gap contacting the first conductive feature; and forming a first etch stop layer over the second low-k dielectric layer, and the first conductive feature.
15. The method of claim 14 , further comprising: forming a second etch stop layer over a third low-k dielectric layer, the first low-k dielectric layer being over the second etch stop layer, wherein the gap extends under a bottom surface of the second etch stop layer.
16. The method of claim 14 , wherein the gap completely separates the first conductive feature from the first low-k dielectric layer.
17. The method of claim 14 , wherein gap extends through the first dielectric layer.
18. The method of claim 6 , wherein the gap extends completely under the metal line.
19. The method of claim 1 , wherein a width of the gap between the upper conductive feature and the upper LK dielectric layer is greater than a width of the gap between the upper conductive feature and the supporting layer.
20. The method of claim 8 , wherein the gap extends between the second low-k dielectric layer and the first dielectric layer.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
August 8, 2016
October 30, 2018
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