Optoelectronic semiconductor chip, optoelectronic component and method for singulating semiconductor chips

1. An optoelectronic semiconductor chip having a carrier and a semiconductor body comprising an active layer provided for generating electromagnetic radiation, wherein the carrier comprises a first major surface facing towards the semiconductor body, a second major surface facing away from the semiconductor body and a side flank arranged between the first major surface and the second major surface, the carrier comprises a structured region for enlarging a total surface area of the side flank, the structured region comprising singulating traces, the structured region comprises a barrier groove, which is circumferential with respect to the carrier, on the side flank, a lateral extent of the barrier groove is between 3 μm and 60 μm inclusive, the barrier groove is spaced apart from the first major surface and from the second major surface, and the optoelectronic semiconductor chip comprises one of the following additional features (i) and (ii), namely: (i) the structured region further comprises on the side flank a plurality of indentations and a lateral extent of the barrier groove is at least twice and at the most ten times as large as a lateral extent of the indentations, or (ii) the structured region comprises an indentation on the side flank, wherein a lateral width of the indentation is between 0.3 μm and 6 μm inclusive and the indentation has a vertical depth which is between 1 times and 5 times the lateral width of the indentation inclusive.

2. The optoelectronic semiconductor chip according to claim 1 , wherein the barrier groove is formed as a depression which is completely circumferential with respect to the carrier.

3. The optoelectronic semiconductor chip according to claim 1 , wherein the structured region is the entire side flank, wherein the carrier is structured in such a manner that the side flank is globally concavely curved or globally convexly curved in the vertical direction.

4. The optoelectronic semiconductor chip according to claim 1 , wherein the structured region is the entire side flank, wherein the carrier is structured in such a manner that as seen in plan view, the first major surface and the second major surface have cross-sections of different sizes, and the side flank forms with the second major surface or with the first major surface an inner acute angle.

5. The optoelectronic semiconductor chip according to claim 1 , wherein the structured region comprises a plurality of indentations and/or a plurality of barrier grooves which are completely circumferential with respect to the carrier in the lateral direction and are spaced apart from one another in the vertical direction.

6. An optoelectronic component comprising a semiconductor chip according to claim 1 and a housing, wherein the housing comprises a cavity, in which the semiconductor chip and a casting compound are arranged in such a manner that the casting compound laterally surrounds the semiconductor chip and completely covers it as seen in plan view.

7. An optoelectronic semiconductor chip having a carrier and a semiconductor body comprising an active layer provided for generating electromagnetic radiation, wherein the carrier comprises a first major surface facing towards the semiconductor body, a second major surface facing away from the semiconductor body and a side flank arranged between the first major surface and the second major surface, the carrier comprises a structured region for enlarging a total surface area of the side flank, the structured region comprising singulating traces, the structured region comprises an indentation and a barrier groove, the barrier groove being circumferential with respect to the carrier, on the side flank, and a lateral extent of the barrier groove is at least twice and at the most 10 times as large as a lateral width of the indentation.

8. The optoelectronic semiconductor chip according to claim 7 , wherein the barrier groove is a circumferential depression being closed in the lateral direction with respect to the carrier, and the lateral extent of the groove is between 3 μm and 60 μm inclusive.

9. An optoelectronic component comprising a housing and a semiconductor chip, the semiconductor chip having a carrier and a semiconductor body comprising an active layer provided for generating electromagnetic radiation, wherein the carrier comprises a first major surface facing towards the semiconductor body, a second major surface facing away from the semiconductor body and a side flank arranged between the first major surface and the second major surface, the carrier comprises a structured region for enlarging a total surface area of the side flank, the structured region comprising singulating traces, the housing comprises a cavity, in which the semiconductor chip and a casting compound are arranged in such a manner that the casting compound laterally surrounds the semiconductor chip and completely covers it as seen in plan view, the structured region comprises a barrier groove which is circumferential with respect to the carrier, and the optoelectronic component comprises one of following features (i) to (iii): (i) the casting compound comprises a first radiation-reflecting partial layer, the first radiation-reflecting partial layer laterally surrounding the carrier, and the first radiation-reflecting partial layer fills the cavity at the most as far as including the barrier groove, (ii) the semiconductor chip is attached by means of an attachment layer to a base surface of the cavity, the attachment layer at least partially covers the base surface of the cavity, the attachment layer engages into the barrier groove, and the barrier groove is formed as a boundary barrier for the attachment layer, or (iii) the barrier groove is spaced apart from the first major surface and from the second major surface, wherein on the side flank, a lateral extent of the barrier groove is between 3 μm and 60 μm inclusive, and the casting compound comprises a first radiation-reflecting partial layer, and wherein the first partial layer laterally surrounds the carrier and, as seen in plan view, the active layer is free of the first partial layer.