Memory systems and memory programming methods

1. A memory system comprising: a bit line; a memory cell coupled with the bitline, and wherein the memory cell is configured to have a plurality of different memory states at different moments in time; a first voltage source configured to provide a first program signal to the bit line and the memory cell at a first moment in time to change the memory cell from a first of the memory states to a second of the memory states; a second voltage source configured to provide a second program signal to the bit line and the memory cell at a second moment in time while the memory cell is in the second memory state; switching circuitry configured to selectively couple each of the first and second voltage sources with the bitline at respective ones of the first and second moments in time and to isolate each of the second and the first voltage sources from the bitline at respective ones of the first and second moments in time; and wherein the first and second program signals have different voltages and the first moment in time occurs before the second moment in time.

2. The memory system of claim 1 wherein the provision of the second program signal enables the memory cell to retain the second memory state after the provision of the first and second program signals to the memory cell.

3. The memory system of claim 1 wherein the memory cell has different electrical resistances corresponding to respective ones of the different memory states.

4. The memory system of claim 3 wherein the memory cell has an increased electrical resistance in the second memory state compared with the electrical resistance of the memory cell in the first memory state.

5. The memory system of claim 1 wherein the memory cell comprises a memory element which comprises dielectric material between plural electrodes, and wherein an electrically conductive structure electrically connects the electrodes while the memory cell is in the first memory state and the electrodes are electrically isolated from one another while the memory cell is in the second memory state.

6. The memory system of claim 1 further comprising detection circuitry configured to detect a change in voltage of the bitline as a result of the change of the memory cell from the first memory state to the second memory state, and wherein the switching circuitry is configured to couple the second voltage source with the bitline and to isolate the first voltage source from the bitline as a result of the detection of the change in voltage of the bitline.

7. The memory system of claim 1 further comprising an access transistor configured to selectively electrically couple the bit line with the memory cell.

8. A memory system comprising: a memory cell configured to have a plurality of different memory states at a plurality of different moments in time, wherein the memory cell comprises a memory element between a plurality of electrodes, the memory element comprises a dielectric material between the electrodes, and the memory element is configured to have different electrical resistances corresponding to the different memory states of the memory cell; program circuitry configured to provide a first program signal to the memory cell to break an electrical connection within the dielectric material which electrically connects the electrodes of the memory cell with one another and the breakage of the electrical connection changes an electrical resistance of the memory cell from a low electrical resistance corresponding to a first of the different memory states to a high electrical resistance corresponding to a second of the different memory states; and wherein the program circuitry is configured to provide a second program signal to the memory cell having the high electrical resistance to enable the memory cell to retain the high electrical resistance after the provision of the first and second program signals to the memory cell.

9. The memory system of claim 8 wherein the program circuitry comprises a driver transistor configured to generate the first and second program signals, and wherein a first voltage biases a gate of the driver transistor during the generation of the first program signal, a second voltage biases a gate of the driver transistor during the generation of the second program signal, and the first and second voltages are different.

10. The memory system of claim 9 wherein the memory cell comprises an access transistor configured to selectively electrically couple the driver transistor with the memory element of the memory cell.

11. The memory system of claim 8 further comprising a bit line between the program circuitry and the memory cell, and wherein the program circuitry comprises: a first voltage source coupled with the bit line to generate the first program signal; and a second voltage source coupled with the bit line to generate the second program signal, and wherein the first and second voltage sources output different voltages.

12. The memory system of claim 8 wherein the program circuitry comprises detection circuitry configured to detect the change of the electrical resistance of the memory cell, and wherein the program circuitry is configured to cease provision of the first program signal to the memory cell and to initiate provision of the second program signal to the memory cell as a result of the detection.

13. A memory system comprising: a memory cell configured to have a plurality of different memory states at different moments in time; program circuitry configured to provide a plurality of program signals to the memory cell to change the memory cell from a first of the different memory states to a second of the different memory states; and wherein the provision of a first of the program signals to the memory cell changes the memory cell from the first memory state to the second memory state and the provision of a second of the program signals to the memory cell enables the memory cell to retain the second memory state after the provision of the first and second program signals to the memory cell.

14. The memory system of claim 13 wherein the memory cell has different electrical resistances corresponding to respective ones of the different memory states and the memory cell has an increased electrical resistance in the second memory state compared with the first memory state.

15. The memory system of claim 13 wherein the memory cell comprises a memory element which comprises dielectric material between plural electrodes, and wherein an electrically conductive structure electrically connects the electrodes while the memory cell is in the first memory state and the electrodes are electrically isolated from one another while the memory cell is in the second memory state.

16. The memory system of claim 13 wherein the program circuitry comprises a driver transistor configured to generate the first and second program signals, a first voltage biases a gate of the driver transistor during the generation of the first program signal, a second voltage biases a gate of the driver transistor during the generation of the second program signal, and the first and second voltages are different.

17. The memory system of claim 16 wherein the memory cell comprises an access transistor configured to selectively electrically couple the driver transistor with a memory element of the memory cell.

18. The memory system of claim 13 further comprising: a bit line between the program circuitry and the memory cell; a first voltage source coupled with the bit line to generate the first program signal; and a second voltage source coupled with the bit line to generate the second program signal, and wherein the first and second voltage sources output different voltages.

19. The memory system of claim 13 wherein the program circuitry is configured to detect the change of the memory cell to the second memory state, to cease provision of the first program signal to the memory cell as a result of the detection, and to initiate provision of the second program signal to the memory cell as a result of the detection.

20. A memory system comprising: a memory cell configured to have a plurality of different memory states at different moments in time; a driver transistor configured to generate a plurality of different program signals which are provided to the memory cell to program the memory cell from a first of the different memory states to a second of the different memory states; wherein a first bias voltage is applied to a gate of the driver transistor during the provision of a first of the different program signals to the memory cell and a second bias voltage is applied to the gate of the driver transistor during the provision of a second of the different program signals to the memory cell, and wherein the first and second bias voltages are different; and wherein the first program signal changes the memory cell from the first memory state to the second memory state and the second program signal enables the memory cell to retain the second memory state after the provision of the first and second program signals to the memory cell.

21. The memory system of claim 20 further comprising detection circuitry configured to detect the change of the memory cell to the second memory state, and wherein the application of the first bias voltage to the gate of the driver transistor is ceased as a result of the detection and the application of the second bias voltage to the gate of the driver transistor is initiated as a result of the detection.

22. The memory system of claim 20 wherein the memory cell has different electrical resistances corresponding to respective ones of the different memory states and the memory cell has an increased electrical resistance in the second memory state compared with the first memory state.

23. The memory system of claim 20 wherein the memory cell comprises a memory element which comprises dielectric material between plural electrodes, and wherein an electrically conductive structure electrically connects the electrodes while the memory cell is in the first memory state and the electrodes are electrically isolated from one another while the memory cell is in the second memory state.

24. The memory system of claim 20 wherein the memory cell comprises an access transistor configured to selectively electrically couple the driver transistor with a memory element of the memory cell.

25. A memory cell programming method comprising: using a source follower amplifier, providing a first program signal to a memory cell in a first of a plurality of different memory states; as a result of the providing the first program signal to the memory cell, changing the memory cell from the first memory state to a second of the different memory states; as a result of the changing the memory cell, changing a load line of the source follower amplifier; and using the source follower amplifier with the changed load line, providing a second program signal to the memory cell in the second memory state.

26. The method of claim 25 wherein the providing the second program signal to the memory cell enables the memory cell to retain the second memory state after the providing the first and second program signals to the memory cell.

27. The method of claim 25 wherein the source follower amplifier comprises a driver transistor and an access transistor, and wherein the changing the load line comprises changing a voltage which is applied to a gate of the driver transistor.

28. The method of claim 27 further comprising providing the access transistor in a conductive state during the providings of the first and second program signals to the memory cell.

29. The method of claim 25 wherein the changing the memory cell from the first memory state to the second memory state increases an electrical resistance of the memory cell.

30. The method of claim 29 wherein the providing the first program signal to the memory cell removes an electrically conductive structure which electrically connects a plurality of electrodes of the memory cell.

31. The method of claim 25 further comprising detecting the changing the memory cell, and wherein the changing the load line is a result of the detecting.

32. A memory system comprising: a bit line; a memory cell coupled with the bitline, and wherein the memory cell is configured to have a plurality of different memory states at different moments in time; a first voltage source configured to provide a first program signal to the bit line and the memory cell at a first moment in time to change the memory cell from a first of the memory states to a second of the memory states; a second voltage source configured to provide a second program signal to the bit line and the memory cell at a second moment in time while the memory cell is in the second memory state; wherein the first and second program signals have different voltages and the first moment in time occurs before the second moment in time; and wherein the provision of the second program signal enables the memory cell to retain the second memory state after the provision of the first and second program signals to the memory cell.

33. A memory system comprising: a bit line; a memory cell coupled with the bitline, and wherein the memory cell is configured to have a plurality of different memory states at different moments in time; a first voltage source configured to provide a first program signal to the bit line and the memory cell at a first moment in time to change the memory cell from a first of the memory states to a second of the memory states; a second voltage source configured to provide a second program signal to the bit line and the memory cell at a second moment in time while the memory cell is in the second memory state; wherein the first and second program signals have different voltages and the first moment in time occurs before the second moment in time; wherein the memory cell comprises a memory element which comprises dielectric material between plural electrodes; and wherein an electrically conductive structure electrically connects the electrodes while the memory cell is in the first memory state and the electrodes are electrically isolated from one another while the memory cell is in the second memory state.

34. A memory system comprising: a memory cell configured to have a plurality of different memory states at different moments in time; a driver transistor configured to generate a plurality of different program signals which are provided to the memory cell to program the memory cell from a first of the different memory states to a second of the different memory states; wherein a first bias voltage is applied to a gate of the driver transistor during the provision of a first of the different program signals to the memory cell and a second bias voltage is applied to the gate of the driver transistor during the provision of a second of the different program signals to the memory cell, and wherein the first and second bias voltages are different; wherein the memory cell comprises a memory element which comprises dielectric material between plural electrodes; and wherein an electrically conductive structure electrically connects the electrodes while the memory cell is in the first memory state and the electrodes are electrically isolated from one another while the memory cell is in the second memory state.