Patentable/Patents/US-10122350
US-10122350

Josephson transmission line (JTL) system

PublishedNovember 6, 2018
Assigneenot available in USPTO data we have
Inventorsnot available in USPTO data we have
Technical Abstract

One embodiment describes a Josephson transmission line (JTL) system. The system includes a plurality of JTL stages that are arranged in series. The system also includes a clock transformer comprising a primary inductor configured to propagate an AC clock signal and a secondary inductor arranged in a series loop with at least two of the plurality of JTL stages. The clock transformer can be configured to propagate a single flux quantum (SFQ) pulse to set a respective one of the plurality of JTL stages in response to a first phase of the AC clock signal and to reset the respective one of the plurality of JTL stages in response to a second phase of the AC clock signal that is opposite the first phase.

Patent Claims
15 claims

Legal claims defining the scope of protection, as filed with the USPTO.

1

1. A Josephson transmission line (JTL) system comprising: a plurality of JTL stages that are arranged in series; and a clock transformer comprising a primary inductor configured to propagate an AC clock signal and a secondary inductor arranged in a series loop with at least two of the plurality of JTL stages, the clock transformer being configured to propagate a single flux quantum (SFQ) pulse to set a respective one of the plurality of JTL stages in response to a first phase of the AC clock signal and to reset the respective one of the plurality of JTL stages in response to a second phase of the AC clock signal that is opposite the first phase.

2

2. The system of claim 1 , wherein the AC clock signal is a quadrature clock signal comprising an in-phase component and a quadrature-phase component, the in-phase and quadrature phase components being out-of-phase by approximately 90°.

3

3. The system of claim 2 , wherein the plurality of JTL stages comprises a first JTL stage coupled to at least one first clock transformer, a second JTL stage coupled to at least one second clock transformer, a third JTL stage coupled to the at least one first clock transformer, and a fourth JTL stage coupled to the at least one second clock transformer, wherein each of the at least one first clock transformer comprises a primary inductor configured to propagate the in-phase component of the AC clock signal, wherein each of the at least one second clock transformer comprises a primary inductor configured to propagate the quadrature-phase component of the AC clock signal.

4

4. The system of claim 3 , wherein the first JTL stage and the second JTL stage are set by the propagation of the SFQ pulse through the first JTL stage and the second JTL stage, respectively, in response to the first phase of the in-phase component and the quadrature-phase component, respectively, of the AC clock signal, and are reset based on the propagation of the SFQ pulse through the third JTL stage and the fourth JTL stage, respectively, in response to the second phase of the in-phase component and the quadrature-phase component, respectively, of the AC clock signal, and wherein the third JTL stage and the fourth JTL stage are set by the propagation of the SFQ pulse through the third JTL stage and the fourth JTL stage, respectively, in response to the second phase of the in-phase component and the quadrature-phase component, respectively, of the AC clock signal, and are reset based on the propagation of the SFQ pulse through the first JTL stage and the second JTL stage, respectively, in response to the first phase of the in-phase component and the quadrature-phase component, respectively, of the AC clock signal.

5

5. The system of claim 1 , further comprising a bias transformer comprising a primary inductor configured to carry a DC bias signal and comprising a secondary inductor that is arranged in series with the secondary inductor of the clock transformer in the series loop, the DC bias signal being inductively provided to the plurality of JTL stages to set one of the plurality of JTL stages in response to the SFQ pulse propagating through the one of the plurality of JTL stages at the first phase of the AC clock signal to propagate the SFQ pulse and to reset the one of the plurality of JTL stages in response to the SFQ pulse propagating through another one of the plurality of JTL stages in the series loop at the second phase of the AC clock signal.

6

6. The system of claim 5 , wherein the bias transformer is a first bias transformer, and wherein the clock transformer comprises at least one first clock transformer associated with an in-phase portion of the AC clock signal and comprising secondary inductors arranged in a series loop with a first portion of the plurality of JTL stages, the system further comprising: at least one second clock transformer associated with a quadrature-phase portion of the AC clock signal and comprising secondary inductors arranged in a series loop with a second portion of the plurality of JTL stages; and a second bias transformer comprising a primary inductor configured to propagate the DC bias signal and comprising a secondary inductor that is arranged in series with the secondary inductor of the second clock transformer in the series loop with the second portion of the plurality of JTL stages.

7

7. The system of claim 1 , wherein the clock transformer is arranged with respect to the AC clock signal such that the plurality of transformers are configured to set one of the plurality of JTL stages in response to the SFQ pulse propagating through the one of the plurality of JTL stages at the first phase of the AC clock signal, and to reset the respective one of the plurality of JTL stages in response to the SFQ pulse propagating through another one of the plurality of JTL stages in the series loop at the second phase of the AC clock signal absent a negative SFQ pulse.

8

8. The system of claim 1 , wherein each of the plurality of JTL stages comprises a first Josephson junction, a second Josephson junction, and an inductor interconnecting the first and second Josephson junctions and being coupled to the secondary inductor of a respective one of the clock transformer, the first and second Josephson junctions and the inductor being arranged as a superconducting quantum interference device (SQUID).

9

9. The system of claim 1 , wherein the plurality of JTL stages are arranged in a series loop to form a flux-shuttle, wherein each of the plurality of JTL stages comprises at least one Josephson junction, the plurality of JTL stages being spaced about the flux shuttle loop and being configured to sequentially trigger the respective at least one Josephson junction in response to the AC clock signal and to propagate the SFQ pulse sequentially and continuously through each of the plurality of JTL stages around the flux-shuttle loop via each of the Josephson junction of each of the respective plurality of JTL stages to provide a DC output signal through an output inductor.

10

10. The system of claim 9 , further comprising an initialization component arranged in the series with the plurality of JTL stages in the flux-shuttle, the initialization component being configured to inject the SFQ pulse into the flux-shuttle.

11

11. A method for propagating unipolar single flux quantum (SFQ) pulses in a Josephson transmission line (JTL) system, the method comprising: providing a DC bias current through a primary inductor of a bias transformer to induce a bias signal via a secondary inductor; providing an AC clock signal through a primary inductor of each of at least one clock transformer, each of the at least one clock transformer comprising a secondary inductor arranged in series with the secondary inductor associated with the bias transformer in a respective at least one series loop with at least two of a plurality of JTL stages of the JTL system; and providing unipolar SFQ pulses at an input of the JTL system, each of the unipolar SFQ pulses being propagated through the plurality of JTL stages based on the bias signal and the AC clock signal to set one of the JTL stages in the at least one series loop and to concurrently reset another one of the JTL stages in the at least one series loop in a sequence.

12

12. The method of claim 11 , wherein providing the AC clock signal comprises: providing an in-phase component of the AC clock signal; and providing a quadrature-phase component of the AC clock signal, the in-phase and quadrature phase components being out-of-phase by approximately 90°.

13

13. The method of claim 12 , wherein the plurality of JTL stages comprises a first JTL stage coupled to at least one first clock transformer, a second JTL stage coupled to at least one second clock transformer, a third JTL stage coupled to the first clock transformer, and a fourth JTL stage coupled to the second clock transformer, wherein providing the in-phase component comprises providing the in-phase component of the AC clock signal to each of the at least one first clock transformer, wherein providing the quadrature-phase component comprises providing the quadrature-phase component of the AC clock signal to each of the at least one second clock transformer.

14

14. The method of claim 13 , wherein, in response to a respective one of the unipolar SFQ pulses propagating through the first JTL stage, the first JTL stage is set and the third JTL stage is reset based on the first phase of the in-phase component of the AC clock signal and the bias signal; wherein, in response to the respective one of the unipolar SFQ pulses propagating through the second JTL stage, the second JTL stage is set and the fourth JTL stage is reset based on the first phase of the quadrature-phase component of the AC clock signal and the bias signal; wherein, in response to the respective one of the unipolar SFQ pulses propagating through the third JTL stage, the third JTL stage is set and the first JTL stage is reset based on the second phase of the in-phase component of the AC clock signal and the bias signal; and wherein, in response to the respective one of the unipolar SFQ pulses propagating through the fourth JTL stage, the fourth JTL stage is set and the second JTL stage is reset based on the second phase of the quadrature-phase component of the AC clock signal and the bias signal.

15

15. The method of claim 11 , wherein the plurality of JTL stages are arranged in the series loop to form a flux-shuttle, wherein each of the plurality of JTL stages comprises at least one Josephson junction, the plurality of JTL stages being spaced about the flux shuttle loop, wherein providing the respective one of the unipolar SFQ pulses comprises sequentially propagating a respective one of the unipolar SFQ pulses sequentially and continuously through each of the plurality of JTL stages around the flux-shuttle loop via each of the Josephson junction of each of the respective plurality of JTL stages to provide a DC output signal through an output inductor.

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Patent Metadata

Filing Date

November 17, 2015

Publication Date

November 6, 2018

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Josephson transmission line (JTL) system — Donald L. Miller | Patentable