Vertically integrated image sensor chips and methods for forming the same

1. A device comprising: a first chip comprising: a first semiconductor substrate; and a first interconnect structure comprising a plurality of metal layers on a side of the first semiconductor substrate; a second chip bonded to the first chip, wherein the second chip comprises: a second semiconductor substrate; and a second interconnect structure comprising a plurality of metal layers on a side of the second semiconductor substrate; a first via penetrating through the first chip to connect to a first metal pad in the second interconnect structure; and a second via penetrating through a dielectric layer in the first interconnect structure to connect to a second metal pad in the first interconnect structure, wherein the first via and the second via are electrically inter-coupled to each other.

2. The device of claim 1 further comprising: a metal pad overlapping a first portion of the first interconnect structure, wherein the metal pad is at a same level as the first semiconductor substrate.

3. The device of claim 2 further comprising a wire bonding stud bump on the metal pad.

4. The device of claim 3 , wherein the wire bonding stud bump comprises a portion at a same level as the first semiconductor substrate.

5. The device of claim 2 , wherein the first interconnect structure comprises: the first portion extending beyond edges of the first semiconductor substrate; and a second portion overlapped by the first semiconductor substrate.

6. The device of claim 1 , wherein the first via has a straight edge continuously extending through the first interconnect structure and the first semiconductor substrate.

7. The device of claim 1 , wherein the first chip comprises an image sensor chip, with an image sensor formed in the first chip.

8. The device of claim 1 , wherein the first via extends from a top surface to a bottom surface of the first chip, and the first via contacts a top surface of the first metal pad, with the first metal pad located in a top metal layer of the second interconnect structure.

9. The device of claim 1 , wherein the first chip is free from Auto Exposure Control (AEC) circuits, Auto Gain Control (AGC) circuits, Auto White Balance (AWB) circuits, and color correction circuits.

10. The device of claim 1 , wherein the first chip further comprises: an image sensor array; and color filters and micro-lenses, wherein the color filters and the second chip are on opposite sides of the first semiconductor substrate.

11. A device comprising: an image sensor chip comprising: a first semiconductor substrate; and an image sensor array in the first semiconductor substrate; a device chip bonded to the image sensor chip, wherein the device chip comprises: a second semiconductor substrate; and an integrated circuit device on a side of the second semiconductor substrate; a first via penetrating through the image sensor chip; and a wire bonding stud bump level with a portion of the first semiconductor substrate, wherein the wire bonding stud bump is electrically connected to devices in the device chip through the first via.

12. The device of claim 11 , wherein the image sensor chip comprises an interconnect structure underlying the first semiconductor substrate, wherein the interconnect structure comprises extension portions extending beyond edges of the first semiconductor substrate, and the extension portions form a ring, and wherein the wire bonding stud bump overlaps a portion of the extension portions.

13. The device of claim 12 , wherein the image sensor chip further comprises a dielectric layer, wherein a bottom surface of the dielectric layer and a bottom surface of the first semiconductor substrate are both in contact with a top surface of the extension portions of the interconnect structure.

14. The device of claim 11 , wherein the wire bonding stud bump comprises a bond stud and a bond wire connected to the bond stud.

15. The device of claim 11 further comprising: a first interconnect structure in the image sensor chip; and a second interconnect structure in the device chip, wherein the first and the second interconnect structures are disposed between the first and the second semiconductor substrates.

16. The device of claim 11 , wherein the image sensor chip comprises a first edge and a second edge misaligned with each other, wherein the first edge is an edge of the first semiconductor substrate, and the second edge is an edge of an interconnect structure of the image sensor chip, and wherein the wire bonding stud bump is disposed between the first edge and the second edge.

17. A device comprising: an image sensor chip comprising: a first semiconductor substrate; and an image sensor array in the first semiconductor substrate; and a device chip bonded to the image sensor chip, wherein the device chip comprises: a second semiconductor substrate; and a logic circuit on a side of the second semiconductor substrate, wherein the logic circuit is selected from the group consisting essentially of an Auto Exposure Control (AEC) circuit, an Auto Gain Control (AGC) circuit, an Auto White Balance (AWB) circuit, a color correction circuit, and combinations thereof, and wherein the logic circuit is configured to process signals of the image sensor array; a via penetrating through the image sensor chip to connect to the device chip; and an electrical connection at a same level as the first semiconductor substrate, wherein the via and the electrical connection electrically connect devices in the image sensor chip to devices in the device chip.

18. The device of claim 17 , wherein the electrical connection comprises a metal pad.

19. The device of claim 17 , wherein the image sensor chip further comprises: an interconnect structure comprising a first portion overlapped by the first semiconductor substrate, and a second portion extending laterally beyond the first semiconductor substrate; and a dielectric layer, wherein a bottom surface of the dielectric layer and a bottom surface of the first semiconductor substrate are both in contact with a top surface of the interconnect structure.

20. The device of claim 17 , wherein the image sensor chip and the device chip are bonded through metal pads in a peripheral region of the image sensor chip.