Data receiver and controller for DDR memory

1. A data receiver for a double data rate (DDR) memory, comprising: a first stage circuit, for receiving a single-ended signal from the DDR memory and converting the single-ended signal into a pair of differential signals; and a second stage circuit, coupled to the first stage circuit, for receiving the differential signals from the first stage circuit and converting the differential signals into an output signal; wherein the first stage circuit and the second stage circuit are implemented in a core voltage domain, and the single-ended signal received by the first stage circuit exceeds the core voltage domain.

2. The data receiver of claim 1 , wherein the first stage circuit further receives a reference voltage, which is compared with the single-ended signal to generate the differential signals.

3. The data receiver of claim 2 , further comprising at least one termination resistor, coupled to the first stage circuit, for generating the reference voltage.

4. The data receiver of claim 1 , wherein the first stage circuit receives a compensation current to improve the linearity of converting the single-ended signal into the differential signals.

5. The data receiver of claim 1 , wherein the first stage circuit comprises: an input differential pair, comprising: a first input transistor, for receiving the single-ended signal; and a second input transistor, for receiving a reference voltage; a switch transistor, coupled to the common source terminal of the first input transistor and the second input transistor; and a load unit, coupled to the drain terminal of the first input transistor and the second input transistor, for providing a resistance.

6. The data receiver of claim 5 , wherein the load unit comprises a resistor or a transistor for generating the resistance.

7. The data receiver of claim 5 , wherein the first stage circuit further comprises: two current sources, each coupled to one of the first input transistor and the second input transistor, for outputting a compensation current to one of the first input transistor and the second input transistor.

8. The data receiver of claim 7 , wherein the compensation current is generated from a bias current, which is generated from the reference voltage.

9. The data receiver of claim 5 , wherein the first input transistor and the second input transistor are thick devices capable of receiving a voltage higher than the core voltage domain.

10. The data receiver of claim 1 , wherein the first stage circuit directly receives the single-ended signal without shifting a voltage level of the single-ended signal before converting the single-ended signal into the differential signals.

11. A controller for a double data rate (DDR) memory, comprising: a data transmitter; and a data receiver, comprising: a first stage circuit, for receiving a single-ended signal from the DDR memory and converting the single-ended signal into a pair of differential signals; and a second stage circuit, coupled to the first stage circuit, for receiving the differential signals from the first stage circuit and converting the differential signals into an output signal; wherein the first stage circuit and the second stage circuit are implemented in a core voltage domain, and the single-ended signal received by the first stage circuit exceeds the core voltage domain.

12. The controller of claim 11 , wherein the first stage circuit further receives a reference voltage, which is compared with the single-ended signal to generate the differential signals.

13. The controller of claim 12 , wherein the data receiver further comprises at least one termination resistor, coupled to the first stage circuit, for generating the reference voltage.

14. The controller of claim 11 , wherein the first stage circuit receives a compensation current to improve the linearity of converting the single-ended signal into the differential signals.

15. The controller of claim 11 , wherein the first stage circuit comprises: an input differential pair, comprising: a first input transistor, for receiving the single-ended signal; and a second input transistor, for receiving a reference voltage; a switch transistor, coupled to the common source terminal of the first input transistor and the second input transistor; and a load unit, coupled to the drain terminal of the first input transistor and the second input transistor, for providing a resistance.

16. The controller of claim 15 , wherein the load unit comprises a resistor or a transistor for generating the resistance.

17. The controller of claim 15 , wherein the first stage circuit further comprises: two current sources, each coupled to one of the first input transistor and the second input transistor, for outputting a compensation current to one of the first input transistor and the second input transistor.

18. The controller of claim 17 , wherein the compensation current is generated from a bias current, which is generated from the reference voltage.

19. The controller of claim 15 , wherein the first input transistor and the second input transistor are thick devices capable of receiving a voltage higher than the core voltage domain.

20. The controller of claim 11 , wherein the first stage circuit directly receives the single-ended signal without shifting a voltage level of the single-ended signal before converting the single-ended signal into the differential signals.

21. A data receiver for a double data rate (DDR) memory, comprising: a first stage circuit, configured to receive a single-ended signal from the DDR memory and convert the single-ended signal into a pair of differential signals; and a second stage circuit, coupled to the first stage circuit and configured to receive the differential signals from the first stage circuit and convert the differential signals into an output signal; wherein the first stage circuit is configured to operate in a core voltage domain, and the single-ended signal exceeds the core voltage domain.