Structures for shallow trench isolation regions and methods for forming shallow trench isolation regions. A trench is etched partially through a device layer of a silicon-on-insulator substrate. A section of the device layer at a bottom of the trench is thermally oxidized to form a shallow trench isolation region in the trench. During the thermal oxidation, another region of the device layer may be concurrently oxidized over a partial thickness and, after removal of the oxide from this device layer region, used as a thinned silicon body. Prior to the thermal oxidation process, this device layer region may be implanted with an oxidation-retarding species that decreases its oxidation rate in comparison with the oxidation rate of the section of the device layer used to form the shallow trench isolation region.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method for forming a shallow trench isolation region, the method comprising: forming spacers on a top surface of a device layer of a silicon-on-insulator substrate, wherein the device layer is comprised of a semiconductor material and has a first thickness; etching a first trench into a portion of the device layer between the spacers and that includes sidewalls that extend partially through the device layer; etching a second trench partially through the device layer of the silicon-on-insulator substrate to expose a section of the device layer at the bottom of the second trench; thermally oxidizing the device layer exposed by the first trench to form a first oxide layer that extends vertically from a buried oxide layer of the silicon-on-insulator substrate through a full thickness of the device layer; implanting the section of the device layer with a first species that reduces an oxidation rate of the semiconductor material of the device layer; and thermally oxidizing a portion of the section of the device layer to thin the section of the device layer to a second thickness that is less than the first thickness and to form a second oxide layer on the section of the device layer, wherein the section of the device layer is arranged on the buried oxide layer of the silicon-on-insulator substrate, and a concentration of the first species is located at an interface between the section of the device layer and the buried oxide layer after the portion of the section of the device layer is thermally oxidized.
2. The method of claim 1 wherein the first oxide layer terminates on the buried oxide layer of the silicon-on-insulator substrate.
3. The method of claim 2 wherein the first oxide layer has curved regions that curve inwardly to intersect the buried oxide layer.
4. The method of claim 3 wherein the device layer includes a tail region that extends beneath one of the curved regions of the first oxide layer, and the tail region is located in a vertical direction between the one of the curved regions of the first oxide layer and the buried oxide layer.
5. The method of claim 4 further comprising: before the device layer is thermally oxidized to form the first oxide layer, implanting the device layer at the sidewalls of the first trench with a second species that increases an oxidation rate of the semiconductor material of the device layer at the sidewalls of the first trench and thereby reduces a size of the tail region.
6. The method of claim 1 wherein the first oxide layer and the second oxide layer are concurrently formed.
7. The method of claim 1 further comprising: removing the second oxide layer from the section of the device layer.
8. The method of claim 7 wherein the section of the device layer provides a body region for device formation.
9. The method of claim 1 wherein the first trench and the second trench extend through a plurality of pad layers formed on the device layer, and at least one of the plurality of pad layers masks underlying sections of the device layer against oxidation when the first oxide layer and the second oxide layer are formed.
10. The method of claim 1 wherein the shallow trench isolation region is formed without chemical-mechanical polishing.
11. The method of claim 1 wherein the shallow trench isolation region is formed without depositing silicon dioxide.
12. The method of claim 1 wherein the first oxide layer terminates at a planar surface with the first trench that is located at or above a plane of the top surface of the device layer.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
May 31, 2017
December 25, 2018
Browse 5M+ US patents with plain-English claim translations and AI-generated analysis.