A semiconductor device having a trench gate structure is configured to include a first n-type semiconductor layer, a p-type semiconductor layer, a trench, an insulating film, a gate electrode, a source electrode and a drain electrode. The first n-type semiconductor layer includes a p-type impurity-containing region configured to contain a p-type impurity at a higher concentration than an n-type impurity. The p-type impurity-containing region is arranged to adjoin the p-type semiconductor layer. In a stacking direction of the first n-type semiconductor layer and the p-type semiconductor layer, the p-type impurity-containing region is provided at a position that does not at least partly overlap with the source electrode and that overlaps with an outer periphery of a bottom face of the trench. This configuration suppresses an increase in capacity between the drain and the source, while improving the breakdown voltage of the semiconductor device.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A semiconductor device having a trench gate structure, comprising: a first n-type semiconductor layer configured to contain an n-type impurity; a p-type semiconductor layer configured to be formed on the first n-type semiconductor layer and contain a p-type impurity and having a trench, the trench is recessed to pass through the p-type semiconductor layer and reaches the first n-type semiconductor layer; an insulating film configured to be arranged to cover a surface of the trench and made of an insulator; a gate electrode configured to be formed on the insulating film in the trench; a source electrode configured to be formed on a second n-type semiconductor layer provided on the p-type semiconductor layer; and a drain electrode configured to be formed on an opposite side to the p-type semiconductor layer across the first n-type semiconductor layer, wherein the first n-type semiconductor layer includes a p-type impurity-containing region configured to contain a p-type impurity at a higher concentration than an n-type impurity, the p-type impurity-containing region is arranged to adjoin the p-type semiconductor layer, and when viewed in a stacking direction of the first n-type semiconductor layer and the p-type semiconductor layer, the p-type impurity-containing region is provided at a position that does not overlap with at least partly the source electrode and that overlaps with an outer periphery of a bottom face of the trench.
2. The semiconductor device according to claim 1 , wherein an average concentration of the p-type impurity in the p-type semiconductor layer at a position that overlaps with the p-type impurity-containing region in the stacking direction is lower than an average concentration of the p-type impurity in the p-type semiconductor layer at a position that does not overlap with the p-type impurity-containing region when viewed in the stacking direction.
3. The semiconductor device according to claim 1 , wherein when Wdi represents a width of the p-type impurity-containing region overlapping with the trench in the stacking direction and Wt represents a width of the trench in the stacking direction, Wdi is equal to or greater than twice a thickness of the insulating film and is less than 2/3 times of Wt.
4. The semiconductor device according to claim 1 , wherein a surface of the p-type semiconductor layer that adjoins the source electrode has a higher concentration of the p-type impurity than a concentration of the p-type impurity in a surface of the p-type semiconductor layer that adjoins the first n-type semiconductor layer.
5. The semiconductor device according to claim 1 , wherein the second n-type semiconductor layer is a first n-type semiconductor region configured to be provided in the p-type semiconductor layer and contain the n-type impurity, and the first n-type semiconductor region is arranged to overlap with the outer periphery of the bottom face of the trench and with the p-type impurity-containing region when viewed in the stacking direction.
6. The semiconductor device according to claim 5 , further comprising: a second n-type semiconductor region configured to be arranged not to overlap with the outer periphery of the bottom face of the trench when viewed in the stacking direction and have a lower concentration of the n-type impurity than a concentration of the n-type impurity in the first n-type semiconductor region.
7. The semiconductor device according to claim 6 , wherein the first n-type semiconductor region has a greater depth in the stacking direction than a depth of the second n-type semiconductor region.
8. The semiconductor device according to claim 6 , wherein an average concentration of the p-type impurity in the p-type semiconductor layer at a position overlapping with the first n-type semiconductor region is lower than an average concentration of the p-type impurity in the p-type semiconductor layer at a position overlapping with the second n-type semiconductor region.
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March 9, 2018
January 8, 2019
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