In a case where a semiconductor layer is epitaxially grown on a step shape formed due to CBL (current blocking layer) formation, the crystallinity of the semiconductor layer lowers. Also, a GaN layer that is epitaxially regrown on the CBL is not formed continuously by epitaxial growth, and therefore the crystallinity of the GaN layer lowers. A vertical semiconductor device manufacturing method is provided that comprises: a step of epitaxially growing a gallium nitride-based n-type semiconductor layer on a gallium nitride-based semiconductor substrate; a step of epitaxially growing a gallium nitride-based p-type semiconductor layer on the n-type semiconductor layer; and a step of ion-implanting p-type impurities to form a p+-type embedded region selectively in a predetermined depth range across the boundary between the n-type semiconductor layer and the p-type semiconductor layer.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A vertical semiconductor device comprising: a gallium nitride-based semiconductor substrate; a gallium nitride-based n-type semiconductor layer provided on the semiconductor substrate; a gallium nitride-based p-type semiconductor layer that is provided on the n-type semiconductor layer and that includes no tail regions, a tail region being a region in which an impurity concentration of majority carriers in a depth direction gradually decreases; and a p + -type embedded region that is provided selectively in a predetermined depth range across a boundary between the n-type semiconductor layer and the p-type semiconductor layer and that includes a region in which an impurity concentration of majority carriers in the depth direction gradually decreases.
2. The vertical semiconductor device according to claim 1 , further comprising: a trench portion that reaches the n-type semiconductor layer located between a pair of the p + -type embedded regions; and an n + -type semiconductor region that is in part of the p-type semiconductor layer and is provided on both sides of the trench portion.
3. The vertical semiconductor device according to claim 1 , further comprising: a trench portion that reaches the n-type semiconductor layer located between a pair of the p + -type embedded regions; and an n + -type semiconductor region that is on the p-type semiconductor layer and is provided on both sides of the trench portion.
4. The vertical semiconductor device according to claim 1 , further comprising: a gate electrode provided above the p-type semiconductor layer; and an n + -type semiconductor region that is in part of the p-type semiconductor layer and is provided in a region different from a region immediately below the gate electrode, wherein the p-type semiconductor layer has, in a region different from the n + -type semiconductor region and different from the region immediately below the gate electrode, an n-type upper drift layer from an uppermost surface of the p-type semiconductor layer to a portion between a pair of the p + -type embedded regions, and the n-type upper drift layer includes n-type impurities and p-type impurities.
5. The vertical semiconductor device according to claim 1 , further comprising: a gate electrode provided above the p-type semiconductor layer; and an n + -type semiconductor region that is on the p-type semiconductor layer and is provided adjacent to the gate electrode, wherein the p-type semiconductor layer has, in a region different from the n + -type semiconductor region and a region immediately below the gate electrode, an n-type upper drift layer from an uppermost surface of the p-type semiconductor layer to a portion between a pair of the p + -type embedded regions, and the n-type upper drift layer includes n-type impurities and p-type impurities.
6. The vertical semiconductor device according to claim 1 , wherein in the region in which an impurity concentration of majority carriers in the depth direction gradually decreases, a depth-direction length required for the impurity concentration to be lowered by an order of magnitude is 50 nm or longer.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
September 29, 2017
January 15, 2019
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