Power consumption in a start-up circuit for a LED-based light bulb may be reduced by digitally switching a transistor of the start-up circuit coupled to the input voltage. When the transistor is digitally switched between on and off, a reduced amount of power is dissipated by the transistor, because it may not enter a saturation region of operation where the resistance of the transistor between drain and source terminals increases. The transistor may be coupled to a voltage regulator for generating one or more output voltages, including a supply voltage for a host controller IC. The transistor may be switched on and off by a digital signal generated by logic circuitry, which may decide to switch the transistor on and off based on a voltage level at an output of the voltage regulator.
Legal claims defining the scope of protection, as filed with the USPTO.
1. An apparatus, comprising: a voltage regulator configured to generate an output voltage for supplying a lighting controller; a current power train comprising a power FET and coupled to the voltage regulator; a gate drive circuit coupled to a gate of the power FET; a logic circuit coupled to the gate drive circuit and configured to operate the power FET as a switching-mode power supply; and a comparator coupled to the logic circuit, wherein the comparator is configured to provide a signal to the logic circuit proportional to a difference between an auxiliary output node voltage and a reference voltage.
2. The apparatus of claim 1 , wherein the power FET comprises a high-voltage (HV) depletion-mode power FET, and wherein the current power train further comprises: a low-voltage (LV) enhancement-mode power FET, wherein a drain of the LV power FET is coupled to a source of the HV power FET; and a diode coupled to the drain of the LV power FET and the source of the HV power FET.
3. The apparatus of claim 2 , wherein the gate drive circuit comprises: an inverter coupled to the gate of the power FET, wherein a power supply input to the inverter comprises a greater of a voltage at the source of the power FET and the output voltage of the voltage regulator.
4. The apparatus of claim 1 , wherein the logic circuitry is configured to digitally switch the power FET based on the comparator signal.
5. The apparatus of claim 3 , wherein the inverter is a complimentary metal-oxide-semiconductor (CMOS) inverter comprising a first and second transistor.
6. The apparatus of claim 5 , wherein the logic circuit generates a control signal to control the first and second transistors.
7. The apparatus of claim 6 , wherein the control signal closes the first transistor, wherein the closing the first transistor couples a voltage applied by the gate control circuit to the LV power FET.
8. The apparatus of claim 7 , wherein the control signal further opens the second transistor, wherein the opening the second transistor disconnects the gate of the LV power FET from ground.
9. The apparatus of claim 1 , further comprising: a sense resistor coupled to a source of the power FET, wherein the sense resistor provides a voltage level to the comparator.
10. The apparatus of claim 9 , wherein the reference voltage corresponds to a first threshold and, when the voltage level provided by the sense resistor reaches the first threshold, the logic circuit operates the gate drive circuit to couple the gate of the power FET to ground.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
August 28, 2017
January 29, 2019
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