A method for fabricating a semiconductor device includes providing a substrate including a cell region including a bit line structure, a bit line spacer and a lower electrode and a peripheral circuit region including first to third impurity regions, forming an interlayer insulating film on the peripheral circuit region, forming a first metal layer on the interlayer insulating film, forming a first trench and a second trench in the first metal layer between the first and second impurity regions, the second trench is disposed between the second and third impurity regions and exposes the interlayer insulating film, forming a first capping pattern on the first trench to form an air gap in the first trench, filling the second trench with a first insulating material, and forming, on the first metal layer, a contact connected to the third impurity region.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method for fabricating a semiconductor device, comprising: providing a substrate including a cell region and a peripheral circuit region, wherein the cell region includes a bit line structure, a bit line spacer formed on both sidewalls of the bit line structure and a lower electrode formed on the bit line structure, wherein the peripheral circuit region is disposed at least partially along a border of the cell region, and wherein the peripheral circuit region includes a first impurity region, a second impurity region and a third impurity region; forming an interlayer insulating film on the peripheral circuit region of the substrate; forming a first metal layer on the interlayer insulating film, wherein the first metal layer is connected to the first impurity region, the second impurity region, and the third impurity region; forming a first trench and a second trench in the first metal layer, wherein the first trench is disposed between the first and second impurity regions and exposes the interlayer insulating film, and the second trench is disposed between the second and third impurity regions and exposes the interlayer insulating film; forming a first capping pattern on the first trench, wherein the first capping pattern is spaced apart from a bottom surface of the first trench forming a first air gap in the first trench; filling the second trench with a first insulating material insulating the second and third impurity regions; and forming, on the first metal layer, a contact connected to the third impurity region, wherein the contact is formed at a first side of the second trench, and wherein the first trench is formed at a second side of the second trench, the first and second sides of the second trench being opposite to each other.
2. The method of claim 1 , wherein the forming of the first capping pattern comprises: filling a portion of the first and second trenches with a second insulating material; forming the first capping pattern on the second insulating material to fully fill the first trench; and selectively removing the second insulating material from the first and second trenches.
3. The method of claim 2 , wherein the forming of the first capping pattern on the second insulating material to fully fill the first trench comprises: filling a portion of the first and second trenches with the second insulating material and then forming a capping film on the first metal layer such that the capping film fully fills the first and second trenches; forming a first mask pattern on the first trench to expose a portion of the capping film on the second trench; forming a pre-capping pattern by selectively removing a portion of the capping film on the second trench by using the first mask pattern as a mask; removing the first mask pattern; and forming the first capping pattern by etching back the pre-capping pattern until an upper surface of the first metal layer is exposed.
4. The method of claim 1 , wherein the first and second trenches extend into the interlayer insulating film.
5. The method of claim 1 , wherein the cell region of the substrate includes a fourth impurity region and a fifth impurity region, wherein the bit line structure is connected to the fourth impurity region, and wherein the bit line spacer includes a first spacer and a second spacer having an etch selectivity with respect to the first spacer, the method further comprising: forming a second metal layer in the cell region of the substrate such that the second metal layer covers the bit line structure and the bit line spacer; forming a third trench in the second metal layer exposing the first spacer and forming a storage node contact, wherein the storage node contact is connected to the fifth impurity region; selectively removing the first spacer, exposed by the third trench, to form a fourth trench in the bit line spacer; forming a second capping pattern, wherein the second capping pattern covers the fourth trench and fills the third trench such that a second air gap is formed in the fourth trench; and forming the lower electrode on the storage node contact, wherein the third trench is formed simultaneously with the first and second trenches.
6. The method of claim 5 , wherein the forming of the first capping pattern comprises: filling a portion of the first to third trenches with a second insulating material; forming a first mask pattern covering the first and second trenches and exposing the third trench; exposing the first spacer by selectively removing the second insulating material, the second insulating material filling a portion of the third trench, by using the first mask pattern as a mask; forming the first capping pattern on the second insulating material of the peripheral circuit region to fully fill the first trench; and selectively removing the second insulating material, the second insulating material filling a portion of the first and second trenches, by using an etch selectivity between the second insulating material and the first capping pattern, wherein the selectively removing of the second insulating material, which fills a portion of the first and second trenches, is performed simultaneously with the forming of the fourth trench.
7. The method of claim 6 , wherein the exposing of the first spacer by selectively removing the second insulating and the forming of the first capping pattern on the second insulating material to fully fill the first trench comprises: forming a capping film on the first and second metal layers to fill a portion of the third trench and to fully fill the first and second trenches; forming a second mask pattern on the first trench to expose a portion of the capping film in the second trench and the third trench; and removing a portion of the capping film in the second trench and the third trench by using the second mask pattern as a mask.
8. The method of claim 1 , wherein the cell region of the substrate includes a fourth impurity region and a fifth impurity region, wherein the bit line structure is connected to the fourth impurity region, and wherein the bit line spacer includes a first spacer and a second spacer having an etch selectivity with respect to the first spacer, the method further comprising: before the forming of the first and second trenches, forming a second metal layer on the cell region of the substrate to cover the bit line structure and the bit line spacer; forming a third trench in the second metal layer exposing the first spacer and forming a storage node contact, wherein the storage node contact is connected to the fifth impurity region; selectively removing the first spacer, exposed by the third trench, forming a fourth trench in the bit line spacer; forming a second capping pattern, the second capping pattern covering the fourth trench and filling the third trench, forming a second air gap in the fourth trench; and forming the lower electrode on the storage node contact.
9. A method for fabricating a semiconductor device, comprising: providing a substrate including a cell region and a peripheral circuit region, wherein the cell region includes a bit line structure, a bit line spacer formed on both sidewalls of the bit line structure and a lower electrode formed on the bit line structure, wherein the peripheral circuit region is disposed at least partially along a border of the cell region, and wherein the peripheral circuit region includes a first impurity region, and a second impurity region therein; forming an interlayer insulating film on the peripheral circuit region of the substrate; forming a first wire pattern connected to the first impurity region and a second wire pattern connected to the second impurity region, the first wire pattern and the second wire pattern being spaced apart from each other on the interlayer insulating film; forming a first trench exposing the interlayer insulating film between the first and second wire patterns, the first trench including a first region and a second region; forming a first capping pattern covering the first region of the first trench, wherein the first capping pattern is spaced apart from a bottom surface of the first trench such that a first air gap is formed in the first region of the first trench; filling the second region of the first trench with a first insulating material; and forming a contact on the second wire pattern, wherein the contact is connected to the second impurity region on a first side of the second region of the first trench, wherein the second region of the first trench is filled with the first insulating material.
10. The method of claim 9 , wherein the forming of the first capping pattern comprises: filling a portion of the first and second regions of the first trench with a second insulating material; forming the first capping pattern on the second insulating material such that the first capping pattern fully fills the first region of the first trench; and selectively removing the second insulating material from the first and second regions of the first trench.
11. The method of claim 10 , wherein the forming of the first capping pattern on the second insulating material comprises: filling a portion of the first and second regions of the first trench with the second insulating material; forming a capping film on the second insulating material and the first and second wire patterns fully filling the first trench; forming a mask pattern on the first trench exposing a portion of the capping film formed on the second region of the first trench; forming a pre-capping pattern by selectively removing a portion of the capping film from the second region of the first trench by using the mask pattern as a mask; removing the mask pattern; and etching back the pre-capping pattern until an upper surface of each of the first and second wire patterns is exposed.
12. The method of claim 9 , wherein the first trench extends into the interlayer insulating film.
13. The method of claim 9 , wherein a length of the first region is longer than a length of the second region, and wherein the length of the first and second regions is measured along a direction in which the first and second wire patterns extend.
14. The method of claim 9 , wherein the cell region of the substrate includes a third impurity region and a fourth impurity region, wherein the bit line structure is connected to the third impurity region, and wherein the bit line spacer includes a first spacer and a second spacer having an etch selectivity with respect to the first spacer, the method further comprising: forming a metal layer on the cell region of the substrate to cover the bit line structure and the bit line spacer; forming a second trench in the metal layer to expose the first spacer and forming a storage node contact, wherein the storage node contact is connected to the fourth impurity region; selectively removing the first spacer, exposed by the second trench, forming a third trench in the bit line spacer; forming a second capping pattern, the second capping pattern covering the third trench and filling the second trench, forming a second air gap in the third trench; and forming the lower electrode on the storage node contact, wherein the third trench is formed simultaneously with the first and second trenches.
15. The method of claim 9 , wherein the cell region of the substrate includes a third impurity region and a fourth impurity region, wherein the bit line structure is connected to the third impurity region, and wherein the bit line spacer includes a first spacer and a second spacer having an etch selectivity with respect to the first spacer, the method further comprising: before forming the first trench, forming a metal layer on the cell region of the substrate covering the bit line structure and the bit line spacer; forming a second trench in the metal layer exposing the first spacer to form a storage node contact, wherein the storage node contact is connected to the fourth impurity region; selectively removing the first spacer, exposed by the second trench, forming a third trench in the bit line spacer; forming a second capping pattern, the second capping pattern covering the third trench and filling the second trench, forming a second air gap in the third trench; and forming the lower electrode on the storage node contact.
16. A method for fabricating a semiconductor device, comprising: providing a substrate including a cell region and a peripheral circuit region, wherein the cell region includes a bit line structure, a first bit line spacer and a second bit line spacer formed on opposite sidewalls of the bit line structure, and a first electrode formed on the bit line structure, wherein the peripheral circuit region is disposed at least partially along a border of the cell region, and wherein the peripheral circuit region includes a first impurity region, and a second impurity region therein; forming an interlayer insulating film on the peripheral circuit region of the substrate; forming a first metal layer on the interlayer insulating film, wherein the first metal layer is connected to the first impurity region and the second impurity region; forming a first wire pattern on the interlayer insulating film, the first wire pattern being connected to the first impurity region; forming a second wire pattern on the interlayer insulating film, the second wire pattern being connected to the second impurity region, wherein the first and second wire patterns are spaced apart from each other; forming a first trench between the first and second wire patterns, the first trench exposing the interlayer insulating film, the first trench including a first region and a second region; forming a first capping pattern on the first region of the first trench to cover the first region of the first trench, wherein the first capping pattern is partially inserted at an opening of the first region of the first trench such that an empty space is formed between a bottom surface of the first region of the first trench and the partially inserted first capping pattern; filling the second region of the first trench with a first insulating material; and forming a contact on the second wire pattern, wherein the contact is connected to the second impurity region on a first side of the second region of the first trench, wherein the second region of the first trench is filled with the first insulating material.
17. The method of claim 16 , wherein a length of the second region of the first trench is shorter than a length of the first region of the first trench.
18. The method of claim 16 , wherein a width of the first wire pattern is different from a width of the second wire pattern.
19. The method of claim 16 , wherein the first insulating material includes silicon nitride (SiN).
20. The method of claim 16 , further comprising a third impurity region in the cell region, wherein the bit line structure contacts the third impurity region.
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August 2, 2017
February 12, 2019
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