A heterostructure device includes a channel layer, a barrier layer disposed on the channel layer, and a first electrode and a second electrode disposed on the barrier layer, respectively. The second electrode includes a p-type semiconductor structure and a raised section disposed on the p-type semiconductor structure, the second electrode includes a Schottky contact and an ohmic contact, the Schottky contact is formed between a top surface of the p-type semiconductor structure and a first bottom surface of the raised section, the ohmic contact is formed between a second bottom surface of the raised section and the barrier layer.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A heterostructure device, comprising: a substrate; a buffer layer disposed on the substrate; a channel layer disposed on the buffer layer; a barrier layer disposed on the channel layer; a first electrode; and a second electrode, wherein the second electrode includes a p-type semiconductor structure and a raised section disposed on the p-type semiconductor structure, the second electrode includes a Schottky contact and an ohmic contact, the Schottky contact is formed between a top surface of the p-type semiconductor structure and a first bottom surface of the raised section, the ohmic contact is formed between a second bottom surface of the raised section and the barrier layer.
2. The heterostructure device as claimed in claim 1 , wherein a depletion region is formed within the channel layer and the barrier layer and underneath the p-type semiconductor structure.
3. The heterostructure device as claimed in claim 1 , wherein a two-dimensional electron gas forms within the channel layer and is devoid of forming in the depletion region.
4. The heterostructure device as claimed in claim 1 , wherein the raised section covers the top surface of the p-type semiconductor structure.
5. The heterostructure device as claimed in claim 1 , wherein the Schottky contact is formed between a side surface of the p-type semiconductor structure and a side surface of the raised section.
6. The heterostructure device as claimed in claim 1 , wherein the p-type semiconductor structure is a p-GaN patterned structure, a p-AlGaN patterned structure, or a combined stacking layers of the p-GaN patterned structure and the p-AlGaN patterned structure.
7. The heterostructure device as claimed in claim 1 , wherein in a cross-sectional view, a contact width between the p-type semiconductor structure and the barrier layer is larger than a contact width between the raised section and the barrier layer.
8. The heterostructure device as claimed in claim 1 , wherein the raised section together with the p-type semiconductor structure form an integral structure disposed on the barrier layer.
9. The heterostructure device as claimed in claim 1 , wherein the substrate is made of at least one material selected from the group consisting of GaAs, AlGaAs, GaAsP, GaP, Si, SiC, metals, sapphire, GaN, AlN, ZnO, MgO, and glass.
10. The heterostructure device as claimed in claim 1 , wherein the channel layer is made of In y1 Al z1 Ga (1-y1-z1) N epitaxial layer, the barrier layer is made of In y2 Al z2 Ga (1-y2-z2) N epitaxial layer, where 0≤y1, y2≤1, 0≤z1, z2≤1, and 0≤(1-y1-z1), (1-y2-z2)<1.
11. The heterostructure device as claimed in claim 1 , wherein the first bottom surface of the raised section is directly contacting the top surface of the p-type semiconductor structure, the second bottom surface of the raised section is directly contacting a top surface of the barrier layer, and a side surface of the p-type semiconductor structure is directly contacting a side surface of the raised section.
12. The heterostructure device as claimed in claim 1 , further comprising a third electrode between the first electrode and the second electrode.
13. The heterostructure device as claimed in claim 1 , wherein the raised drain section is partially surrounding the p-type semiconductor structure, and a bandgap of the channel layer is less than a bandgap of the barrier layer.
14. The heterostructure device as claimed in claim 12 , wherein the first electrode is a source electrode, the second electrode is a drain electrode, and the third electrode is a gate electrode.
15. The heterostructure device as claimed in claim 1 , wherein in a cross-sectional view, a width of the first bottom surface of the raised section is greater than a width of the second bottom surface of the raised section.
16. The heterostructure device as claimed in claim 1 , wherein a shape of the p-type structure in a top view comprises a continuous strip.
17. The heterostructure device as claimed in claim 1 , wherein a shape of the p-type structure in a top view comprises a plurality of strips disposed at intervals.
18. The heterostructure device as claimed in claim 1 , wherein the first electrode and the raised section comprises a same material.
19. The heterostructure device as claimed in claim 18 , wherein the first electrode and the raised section, being of the same material, comprises a metal.
20. The heterostructure device as claimed in claim 1 , wherein the channel layer comprises a first group IIIA-VA compound semiconductor material and the barrier layer comprises a second group IIIA-VA compound semiconductor material.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
January 4, 2017
February 12, 2019
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