A device and method for fabricating an integrated circuit (IC) chip is disclosed. The method includes depositing a first thin film resistor material on a first inter-level dielectric (ILD) layer; depositing an etch retardant layer overlying the first thin film resistor material; and patterning and etching the etch retardant layer and the first thin film resistor material to form a first resistor. The method continues with depositing a second ILD layer overlying the first resistor; and patterning and etching the second ILD layer using a first etch chemistry to form vias through the second ILD layer and the etch retardant layer to the first resistor. The etch retardant layer is selective to a first etch chemistry and the thickness of the etch retardant layer is such that the via etching process removes substantially all exposed portions of the etch retardant layer and substantially prevents consumption of the underlying first thin film resistor material.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method for fabricating an integrated circuit (IC) chip, the method comprising: depositing a first thin film resistor material on a first inter-level dielectric (ILD) layer; depositing an etch retardant layer overlying the first thin film resistor material; patterning and etching the etch retardant layer and the first thin film resistor material to form a first resistor; depositing a second ILD layer overlying the first resistor; patterning and etching the second ILD layer using a first etch chemistry to form vias through the second ILD layer and the etch retardant layer to the first resistor, wherein the etch retardant layer is selective to the first etch chemistry and the thickness of the etch retardant layer is such that the via etch removes substantially all exposed portions of the etch retardant layer and substantially prevents consumption of the underlying first thin film resistor material, and prior to depositing the first thin film resistor material: depositing a second thin film resistor material on a third ILD layer that overlies a metallization layer; patterning and etching the second thin film resistor material to form a second resistor; depositing the first ILD layer overlying the second resistor; and patterning and etching the first ILD layer to form head regions for the second resistor; wherein depositing the first thin film resistor material comprises depositing the first thin film resistor material in the head regions, the patterning and etching the etch retardant layer and the first thin film resistor material further forms resistors heads for the second resistor, and the patterning and etching the second ILD layer further forms vias through the first ILD layer and the etch retardant to the head regions for the second resistor.
2. The method as recited in claim 1 wherein depositing the etch retardant layer comprises depositing a first dielectric, depositing an etch-retardant material and depositing a second dielectric.
3. The method as recited in claim 1 wherein the etch retardant material is selected from a group comprising silicon nitride and silicon carbide.
4. The method as recited in claim 2 wherein the etch retardant material has a thickness in the range of between about 50-700 Angstroms.
5. The method as recited in claim 1 further comprising, prior to depositing the second thin film resistor material: providing a semiconductor substrate on which a plurality of semiconductor devices have been formed; depositing a fourth ILD layer directly overlying the semiconductor substrate; forming a contact that extends through the fourth ILD layer; forming the metallization layer that is coupled to the contact; and depositing the third inter-level dielectric; wherein the patterning and etching the second ILD layer further forms vias through the first, second and third ILD layers to the contact.
6. The method as recited in claim 1 wherein the first thin film resistor material and the second thin film resistor material each comprises a material selected from a group comprising silicon chromium, nickel chromium, chromium silicon oxide, silicon oxynitride and Cr V C W Si X N Y O Z , where V, W, X, Y and Z are between zero and four inclusive.
7. The method as recited in claim 1 wherein the first etch chemistry is selected from a group comprising argon, oxygen, CF Y , C X F Y and C X H Y F Z , where each of X, Y and Z is equal to a number between 1 and 4 inclusive.
8. A method for fabricating an integrated circuit (IC) chip, the method comprising: depositing a first thin film resistor material on a first inter-level dielectric (ILD) layer; depositing an etch retardant layer overlying the first thin film resistor material; patterning and etching the etch retardant layer and the first thin film resistor material to form a first resistor; depositing a second ILD layer overlying the first resistor; patterning and etching the second ILD layer using a first etch chemistry to form vias through the second ILD layer and the etch retardant layer to the first resistor, wherein the etch retardant layer is selective to the first etch chemistry and the thickness of the etch retardant layer is such that the via etch removes substantially all exposed portions of the etch retardant layer and substantially prevents consumption of the underlying first thin film resistor material, wherein patterning and etching the etch retardant layer and the first thin film resistor material comprises: depositing and patterning a first photoresist layer that overlies the etch retardant layer using a first mask; etching the etch retardant layer; ashing the remaining portions of the first photoresist layer and cleaning the IC chip; depositing and patterning a second photoresist layer that overlies the etch retardant layer and the first thin film resistor material using the first mask; etching the first thin film resistor material; and ashing the remaining portions of the second photoresist layer and cleaning the IC chip.
9. A method for fabricating an integrated circuit (IC) chip, the method comprising: providing a semiconductor substrate on which a plurality of semiconductor devices have been formed; depositing a first inter-level dielectric (ILD) layer directly overlying the semiconductor substrate; forming a contact that extends through the first ILD layer; forming a metallization layer that is coupled to the contact; and depositing a second ILD; depositing a first thin film resistor material on the second ILD layer; patterning and etching the first thin film resistor material to form a first resistor; depositing a third ILD layer overlying the first resistor; patterning and etching the third ILD layer to form head regions for the first resistor; depositing a second thin film resistor material on the third ILD layer; depositing an etch retardant layer overlying the second thin film resistor material; patterning and etching the etch retardant layer and the second thin film resistor material to form a second resistor and resistor heads for the first resistor; depositing a fourth ILD layer overlying the second resistor; patterning the fourth ILD layer for forming vias to the heads of the first resistor, the second resistor and the contact; and simultaneously etching, using a first etch chemistry, vias through, where necessary, the fourth ILD, the third ILD, the second ILD and the etch retardant layer to the first resistor, the heads of the second resistor and the contact wherein the etch retardant layer is selective to the via etch and the thickness of the etch retardant layer is such that the via etch removes substantially all exposed portions of the etch retardant layer and substantially prevents consumption of the underlying first and second thin film resistor materials.
10. A integrated circuit (IC) chip comprising: a metallization layer; a first dielectric layer directly overlying the metallization layer; a first thin film resistor formed on the first dielectric layer; a second dielectric layer overlying the first thin film resistor a second thin film resistor formed on the second dielectric layer, the second thin film resistor comprising a resistor material wherein a portion of the resistor material also forms resistor heads through the second dielectric layer to the first thin film resistor; an etch retardant layer overlying the resistor material of both the second thin film resistor and the resistor heads; a third dielectric layer overlying the second thin film resistor; a first via and a second via extending through the third dielectric layer and the etch retardant layer to the second thin film resistor; a third via and a fourth via extending through the third dielectric layer, part of the second dielectric layer and the etch retardant layer to the resistor heads of the first thin film resistor; and a fifth via extending through the third dielectric layer, the second dielectric layer, and the first dielectric layer to contact the metallization layer.
11. The IC chip as recited in claim 10 , wherein the first thin film resistor and the resistor material comprise a material selected from a group comprising silicon chromium, nickel chromium, chromium silicon oxide, silicon oxynitride and Cr V C W Si X N Y O Z , where V, W, X, Y and Z are each between zero and four inclusive.
12. The IC chip as recited in claim 10 , wherein the etch retardant layer comprises a tri-layer of a first dielectric, an etch retardant material and a second dielectric.
13. The IC chip as recited in claim 10 , wherein the etch retardant material comprises a material selected from a group comprising SiN, SiON, SiC.
14. The IC chip as recited in claim 10 , wherein the etch retardant material has a thickness in the range of between about 50-700 Angstroms.
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July 11, 2017
February 19, 2019
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