Patentable/Patents/US-10211751
US-10211751

Non-polar rectifying circuit

PublishedFebruary 19, 2019
Assigneenot available in USPTO data we have
Inventorsnot available in USPTO data we have
Technical Abstract

A non-polar rectifying circuit includes two input terminals, two output terminals, two P-channel MOS transistors, and two N-channel MOS transistors. The two input terminals are respectively connected with a drain of one of the two P-channel MOS transistors and a drain of one of the two N-channel MOS transistors. One of the output terminals is electrically connected with the source of two P-channel MOS transistors, and the other output terminal is electrically connected with the source of two N-channel MOS transistors. In application, regardless of the two input terminals which is the positive polarity or negative polarity, one of the output terminals will output high level, and another will also output low level. As a result, it make the power plug no need to divide the positive and negative, which can reduce the installation time of LED lamps, especially for installing a large number of LED lightings.

Patent Claims
3 claims

Legal claims defining the scope of protection, as filed with the USPTO.

1

1. A non-polar rectifying circuit, comprising: a first input terminal; a second input terminal; a first output terminal; a second output terminal; a first P-channel MOS transistor; a second P-channel MOS transistor; a first N-channel MOS transistor; a second N-channel MOS transistor, and the first input terminal is connected with a drain of the first P-channel MOS transistor and a drain of the first N-channel MOS transistor, the second input terminal is connected with a drain of the second P-channel MOS transistor and a drain of the second N-channel MOS transistor, the first output terminal is electrically connected with the sources of the first and second P-channel MOS transistors, the second output terminal is electrically connected with the sources of the first and second N-channel MOS transistors; wherein the second input terminal is electrically connected to a gate of the first P-channel MOS transistor by a fourth regulator, wherein an anode of the fourth regulator is electrically connected to the second input terminal, a cathode of the fourth regulator is connected to the gate of the first P-channel MOS transistor, and the first input terminal is electrically connected to a gate of the second P-channel MOS transistor by a third regulator, an anode of the third regulator is electrically connected to the first input terminal, a cathode of the third regulator is electrically connected to the gate of the second P-channel MOS transistor; wherein the first input terminal is electrically connected to a gate of the second N-channel MOS transistor by a first regulator, wherein a cathode of first regulator is electrically connected to the first input terminal, an anode of the first regulator is electrically connected to the gate of the second N-channel MOS transistor, and the second input terminal is electrically connected to a gate of the first N-channel MOS transistor by a second regulator, a cathode of the second regulator is electrically connected to the second input terminal, an anode of the second regulator is electrically connected with the gate of the first N-channel MOS transistor; wherein the cathodes of the third regulator and the fourth regulator are electrically connected through a second protection resistor and anodes of the first regulator and the second regulator are electrically connected through a first protection resistor.

2

2. The non-polar rectifying circuit as claimed in claim 1 , wherein a voltage regulation value of all regulators is greater than a difference between an input value of the input terminal and a threshold voltage value of the P-channel or N-channel MOS transistors.

3

3. The non-polar rectifying circuit as claimed in claim 1 , wherein the gate of the first P-channel MOS transistor is electrically connected to the gate of the gate of the second P-channel MOS transistor by the second protection resistor, the gate of the first N-channel MOS transistor is electrically connected to the gate of the second N-channel MOS transistor by the first protection resistor.

Classification Codes (CPC)

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Patent Metadata

Filing Date

December 15, 2016

Publication Date

February 19, 2019

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