Semiconductor device, and unique ID generation method

A semiconductor device according to one embodiment includes a unique ID generation circuit configured to generate a unique ID using a memory array including a plurality of complementary cells, each of the complementary cells includes first and second memory cells MC1 and MC2. The unique ID generation circuit uses, when data in the complementary cell read out in a first state in which an initial threshold voltage of the first memory cell MC1 has been virtually offset and data in the complementary cell read out in a second state in which an initial threshold voltage of the second memory cell MC2 has been virtually offset coincide with each other, the data in the complementary cell as the unique ID.