A sample and hold system, for capturing and reading at least one input signal. The system comprises a readout device, a controller, an array of segments comprising a plurality of unit cells and a dummy unit cell, and segment switches between the segments and the readout device. The controller is adapted for controlling the system such that: during an acquisition phase a trace of samples is taken from the input signal and held in the unit cells; during a readout phase the samples in the unit cells or in the dummy unit cells of a segment are read out by readout device; after opening or closing the segment switches the dummy unit cell, is the first cell which is read out by the readout device.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A sample and hold system, for capturing and reading a trace of at least one input signal, the sample and hold system comprising a readout device, a controller, an array of segments, each segment comprising a plurality of unit cells and a dummy unit cell, and access switches for controlling the access to the unit cells and the dummy unit cells, wherein at least part or all of the access switches are segment switches which are present between the segments and the readout device, wherein the controller is adapted for controlling the sample and hold system, such that during an acquisition phase a trace of samples is taken from the input signal and held in the unit cells and such that during a readout phase the samples held in the unit cells or in the dummy unit cells are read out by the readout device, wherein the controller is adapted for controlling the sample and hold system, such that the dummy unit cells are sampled in a period when there is no input signal, and such that after configuring the segment switches to connect a segment to the reading device, the dummy unit cell, is the first cell which is read out by the readout device resulting in a readout value wherein the sample and hold system is adapted for ignoring the readout value of the dummy unit cells during further processing.
2. A sample and hold system according to claim 1 , wherein the controller is adapted for controlling the access switches using control signals derived from a sample clock for sampling the input signal.
3. A sample and hold system according to claim 2 , wherein the control signals are a delayed version of the sample clock.
4. A sample and hold system according to claims 2 , wherein each segment comprises a digital feedback loop configured to indicate, during the acquisition phase, to the unit cell which is accessed first in the segment that the last unit cell of that segment, before switching to another segment, is accessed.
5. A sample and hold system according to claim 1 wherein each unit cell and dummy unit cell is comprising a capacitor and wherein the capacitors are configured for holding the samples taken from the input signal and wherein for each of the segments the first terminals of the capacitors are connected with one side of one of the segment switches which is connected with the other side to the readout device.
6. A sample and hold system according to claim 5 , wherein the controller moreover is configured for controlling the sample and hold system such that during a parasitic equalization phase, in between the acquisition phase and the readout phase at least part of the segment switches are closed.
7. A sample and hold system according to claim 1 wherein the readout device comprises an analog to digital convertor configured for digitizing, during the readout phase, the samples in the unit cells into digitized sample values.
8. A sample and hold system according to claim 1 , wherein the unit cells and dummy unit cells are organized in rows and columns wherein each segment corresponds with a row comprising unit cells and a dummy unit cell.
9. A sample and hold system according to claim 1 wherein the readout device comprises an operational amplifier and wherein the unit cells and the dummy unit cell are connected with an input terminal of the operational amplifier.
10. A sample and hold system according to claim 9 , the sample and hold system comprising for each segment a segment read switch in between the second terminals of the unit cells and of the dummy unit cell and an output of the operational amplifier.
11. An application system comprising a signal generation device and a sample and hold system according to claim 1 wherein the signal generation device is adapted for generating at least one output signal and wherein the at least one output signal is the at least one input signal of the sample and hold system.
12. An optical detector, the optical detector comprising a sample and hold system according to claim 1 and an array of optical sensors, each optical sensor comprising an input for detecting an optical signal and an output for generating an output signal which is representative for the detected optical signal, wherein the outputs of the optical sensors are the input signals of the sample and hold system.
13. A method for capturing and reading a trace of an input signal using a sample and hold system which comprises an array of segments, each segment comprising a plurality of unit cells and a dummy unit cell, and access switches for controlling the access to the unit cells and the dummy unit cells, wherein at least part or all of the access switches are segment switches which are present between the segments and the readout device, the method comprising: an acquisition phase wherein samples are taken from the input signal and held in unit cells of different segments, wherein the dummy unit cells are sampled when there is no input signal, and wherein during a readout phase the samples in the unit cells are read out segment by segment by a readout device by configuring the segment switches to connect a segment to the reading device, wherein after configuring the segment switches to connect a segment to the reading device, the dummy unit cell, is the first cell which is read out by the readout device resulting in a readout value, and that the readout value of the dummy unit cells is ignored during further processing.
14. A method according to claim 13 , the method furthermore comprising a parasitic equalization phase in between the acquisition phase and the readout phase, wherein during the parasitic equalization phase segment switches, which are configured for connecting the segments with the readout device, are closed.
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February 23, 2018
April 2, 2019
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