Operation of a multi-slice processor that includes execution slices and load/store slices coupled via a results bus includes: receiving, by an execution slice, a producer instruction, including: storing, in an entry of an issue queue, the producer instruction; and storing, in a register, an issue queue entry identifier representing the entry of the issue queue in which the producer instruction is stored; receiving, by the execution slice, a source instruction, the source instruction dependent upon the result of the producer instruction, including: storing, in another entry of the issue queue, the source instruction and the issue queue entry identifier of the producer instruction; determining in dependence upon the issue queue entry identifier of the producer instruction that the producer instruction has issued from the issue queue; and responsive to the determination that the producer instruction has issued from the issue queue, issuing the source instruction from the issue queue.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A multi-slice processor comprising: a plurality of execution slices; a dispatcher; and a plurality of load/store slices, wherein each of the plurality of load/store slices are coupled to at least one of the plurality of execution slices via a results bus, and the multi-slice processor is configured for: receiving, by an execution slice of the plurality of execution slices from the dispatcher, a producer instruction, including: storing, in an entry of an issue queue in the execution slice, the producer instruction; and storing, in a register in the execution slice, an issue queue entry identifier representing the entry of the issue queue in which the producer instruction is stored; receiving, by the execution slice from the dispatcher, a source instruction, the source instruction dependent upon a result of the producer instruction, including: retrieving, from the register, the issue queue entry identifier representing the entry of the issue queue in which the producer instruction is stored; and storing, in another entry of the issue queue, the source instruction and the issue queue entry identifier representing the entry of the issue queue in which the producer instruction is stored; maintaining, by the issue queue, a one-hot bit string indicating a most recent entry issued; determining, by the execution slice, in dependence upon the issue queue entry identifier of the producer instruction that the producer instruction has issued from the issue queue, wherein determining that the producer instruction has issued from the issue queue further comprises determining that the one-hot bit string indicates the most recent entry issued is the entry in which the producer instruction is stored; and responsive to determining that the producer instruction has issued from the issue queue, issuing, by the execution slice, the source instruction from the issue queue.
2. The multi-slice processor of claim 1 further configured for: periodically providing by the issue queue to the dispatcher, available entries in the issue queue.
3. The multi-slice processor of claim 1 wherein: receiving the producer instruction further comprises receiving, with the producer instruction, the issue queue entry identifier.
4. The multi-slice processor of claim 1 wherein: storing, in the register, the issue queue entry identifier representing the entry of the issue queue in which the producer instruction is stored comprises storing an identifier of the producer instruction in the register; and wherein issuing, by the execution slice, the source instruction from the issue queue comprises issuing the source instruction without snooping the identifier of the producer instruction from the results bus.
5. The multi-slice processor of claim 1 wherein: each execution slice includes an instruction queue, a general purpose register, a history buffer, and an arithmetic execution unit, wherein each execution slice is associated with a load-store slice to form a single slice of the multi-slice processor.
6. An apparatus comprising: a multi-slice processor that includes a plurality of execution slices, a dispatcher, and a plurality of load/store slices, wherein each of the plurality of load/store slices are coupled to at least one of the plurality of execution slices via a results bus; and a computer memory operatively coupled to the multi-slice processor, wherein the multi-slice processor is configured for: receiving, by an execution slice of the plurality of execution slices from the dispatcher, a producer instruction, including: storing, in an entry of an issue queue in the execution slice, the producer instruction; and storing, in a register in the execution slice, an issue queue entry identifier representing the entry of the issue queue in which the producer instruction is stored; receiving, by the execution slice from the dispatcher, a source instruction, the source instruction dependent upon a result of the producer instruction, including: retrieving, from the register, the issue queue entry identifier representing the entry of the issue queue in which the producer instruction is stored; and storing, in another entry of the issue queue, the source instruction and the issue queue entry identifier representing the entry of the issue queue in which the producer instruction is stored; maintaining, by the issue queue, a one-hot bit string indicating a most recent entry issued; determining, by the execution slice, in dependence upon the issue queue entry identifier of the producer instruction that the producer instruction has issued from the issue queue, wherein determining that the producer instruction has issued from the issue queue further comprises determining that the one-hot bit string indicates the most recent entry issued is the entry in which the producer instruction is stored; and responsive to determining that the producer instruction has issued from the issue queue, issuing, by the execution slice, the source instruction from the issue queue.
7. The apparatus of claim 6 , wherein the multi-slice processor is further configured for: periodically providing by the issue queue to the dispatcher, available entries in the issue queue.
8. The apparatus of claim 6 wherein: receiving the producer instruction further comprises receiving, with the producer instruction, the issue queue entry identifier.
9. The apparatus of claim 6 wherein: storing, in the register, the issue queue entry identifier representing the entry of the issue queue in which the producer instruction is stored comprises storing an identifier of the producer instruction in the register; and wherein issuing, by the execution slice, the source instruction from the issue queue comprises issuing the source instruction without snooping the identifier of the producer instruction from the results bus.
10. The apparatus of claim 6 wherein: each execution slice includes an instruction queue, a general purpose register, a history buffer, and an arithmetic execution unit, wherein each execution slice is associated with a load-store slice to form a single slice of the multi-slice processor.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
December 15, 2015
April 23, 2019
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