Structures and formation methods of a chip package are provided. The chip package includes a semiconductor die and a package layer partially or completely encapsulating the semiconductor die. The chip package also includes a polymer layer over the semiconductor die and the package layer. The chip package further includes a dielectric layer over the polymer layer. The dielectric layer is substantially made of a semiconductor oxide material. In addition, the chip package includes a conductive feature in the dielectric layer electrically connected to a conductive pad of the semiconductor die.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A chip package, comprising: a semiconductor die having a topmost surface and a bottommost surface; a package layer at least partially encapsulating the semiconductor die; a polymer layer over the semiconductor die and the package layer, an interface between the polymer layer and the package layer being below the topmost surface of the semiconductor die and above the bottommost surface of the semiconductor die; a dielectric layer over the polymer layer; and a conductive feature in the dielectric layer, wherein top surfaces of the dielectric layer and the conductive feature are coplanar.
2. The chip package of claim 1 , wherein the dielectric layer is semiconductor oxide material.
3. The chip package of claim 1 , wherein the polymer layer is in direct contact with the conductive feature.
4. The chip package as claimed in claim 1 , wherein the polymer layer is in direct contact with the package layer.
5. The chip package as claimed in claim 1 , wherein the dielectric layer is in direct contact with the polymer layer.
6. The chip package as claimed in claim 1 , further comprising a second semiconductor die, wherein the package layer at least partially encapsulating the second semiconductor die.
7. The chip package as claimed in claim 6 , wherein the second semiconductor die is electrically coupled to the semiconductor die through a second conductive feature in the dielectric layer.
8. The chip package of claim 1 , further comprising: a second polymer layer over the dielectric layer; and a conductive connector over the second polymer layer electrically connected to the conductive feature.
9. The chip package as claimed in claim 8 , further comprising an etch stop layer between the dielectric layer and a second dielectric layer.
10. A chip package, comprising: a semiconductor die; a package layer at least partially encapsulating the semiconductor die; a polymer layer over the semiconductor die and the package layer; a dielectric layer contacting the polymer layer; and a conductive feature fully embedded in the dielectric layer, wherein the conductive feature is electrically connected to a conductive pad of the semiconductor die; and a second semiconductor die, wherein the package layer at least partially encapsulating the second semiconductor die.
11. The chip package as claimed in claim 1 , wherein the second semiconductor die is electrically coupled to the semiconductor die through a second conductive feature in the dielectric layer.
12. The chip package as claimed in claim 10 , further comprising: a second dielectric layer over the dielectric layer and the conductive feature wherein the second dielectric layer includes a semiconductor oxide material; and a second conductive feature in the second dielectric layer electrically connected to the conductive feature.
13. The chip package as claimed in claim 12 , further comprising an etch stop layer between the dielectric layer and the second dielectric layer.
14. The chip package as claimed in claim 10 , die wherein top surfaces of the dielectric layer and the conductive feature are coplanar.
15. The chip package as claimed in claim 10 , wherein the dielectric layer is not made of a polymer material.
16. A method for forming a chip package, comprising: forming a molding compound layer over a first semiconductor die and a second semiconductor die to at least partially encapsulate the first semiconductor die; forming a polymer layer over the first semiconductor die and the molding compound layer; forming a dielectric layer over the polymer layer; patterning the dielectric layer to have first openings and patterning the polymer layer to have second openings; and filling the first openings and the second openings with a conductor to form a conductive feature electrically connecting a contact pad on the first semiconductor die to a contact pad on the second semiconductor die.
17. The method of claim 16 , further comprising planarizing the polymer layer before forming the dielectric layer.
18. The method for forming a chip package as claimed in claim 16 , wherein the dielectric layer is formed using a vapor deposition process.
19. The method for forming a chip package as claimed in claim 16 , further comprising: planarizing the conductor to remove the conductor outside of respective first openings such that remaining portion of the conductor form the conductive feature.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
July 17, 2017
April 23, 2019
Browse 5M+ US patents with plain-English claim translations and AI-generated analysis.