A sense structure may include sense amplifiers each having measuring and reference terminals for receiving a measuring and a reference current, respectively, output circuitry for providing an output voltage based upon the measuring and reference currents, and voltage regulating circuitry in cascade configuration for regulating a voltage at the measuring and reference terminals. The regulating circuitry may include measuring and regulating transistors and a reference regulating transistor having a first conduction terminal coupled with the measuring terminal and with the reference terminal, respectively, a second conduction terminal coupled with the output circuitry and a control terminal coupled with a biasing terminal. Biasing circuitry is for providing a biasing voltage to the biasing terminal, and common regulating circuitry is for regulating the biasing voltage. Each sense amplifier may also include local regulating circuitry for regulating the biasing voltage applied to the biasing terminal.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A circuit comprising: a memory cell; a biasing stage; and a sense amplifier coupled to the memory cell and configured to generate an output signal in an output terminal, the sense amplifier comprising: a measuring transistor having a first load path terminal coupled to the memory cell; a reference transistor having a first load path terminal coupled to a reference cell; a local capacitor coupled to a gate of the measuring transistor and to a gate of the reference transistor; a first switch coupled between the local capacitor and the biasing stage; a second switch coupled between the measuring transistor and the reference transistor; and an output stage coupled to the measuring transistor and further coupled to the reference transistor, the output stage configured to generate the output signal during a sensing state based on a memory content of the memory cell; wherein during a rest state, the first switch is configured to be on and the second switch is configured to be off; wherein during a pre-charge state after the rest state, the first switch is configured to be off and the second switch is configured to be on; and wherein during a sensing state after the pre-charge state, the first switch is configured to be off and the second switch is configured to be off.
2. The circuit of claim 1 , wherein the memory cell comprises a floating gate MOS transistor.
3. The circuit of claim 1 , wherein the sense amplifier further comprises a local resistor coupled in series with the local capacitor.
4. The circuit of claim 1 , wherein in the pre-charge state, a current flowing through the reference transistor charges a stray capacitance coupled to the measuring transistor.
5. The circuit of claim 1 , wherein the output stage comprises: a first transistor coupled between a first supply node and the measuring transistor; and a second transistor coupled between the first supply node and the reference transistor, the second transistor having a gate coupled to a gate of the first transistor.
6. The circuit of claim 5 , wherein during the pre-charge state, a current flowing through the second transistor charges a stray capacitance coupled to the measuring transistor.
7. The circuit of claim 5 , wherein the output stage further comprises: a third transistor coupled between the first transistor and a second supply terminal; a fourth transistor coupled between the third transistor and the second supply terminal; a fifth transistor coupled between the second transistor and the second supply terminal; and a sixth transistor coupled between the fifth transistor and the second supply terminal, wherein the fifth transistor is coupled to the output terminal.
8. The circuit of claim 7 , wherein the first transistor, second transistor, third transistor, and fifth transistor are PMOS transistors; and the fourth transistor, sixth transistor, measuring transistor, and reference transistor and second switch are NMOS transistor.
9. A circuit comprising: a floating gate MOS transistor; a biasing stage; and a sense amplifier coupled to the floating gate MOS transistor and configured to generate an output signal in an output terminal, the sense amplifier comprising a measuring transistor having a first load path terminal coupled to the floating gate MOS transistor; a reference transistor having a first load path terminal coupled to a reference cell; a local capacitor coupled to a gate of the measuring transistor and to a gate of the reference transistor; a first switch coupled between the local capacitor and the biasing stage; a second switch coupled between the first load path terminal of the measuring transistor and the first load path terminal of the reference transistor; and an output stage coupled to a second load path terminal of the measuring transistor and further coupled to a second load path terminal of the reference transistor, the output stage configured to generate the output signal during a sensing state based on a memory content of the floating gate MOS transistor; wherein during a pre-charge state, the sense amplifier is configured to turn on the second switch and turn off the first switch such a current flowing through the reference transistor charges a stray capacitance coupled to the first load path terminal of the measuring transistor by flowing through the second switch.
10. The circuit of claim 9 , wherein: during a rest state before the pre-charge state, the sense amplifier is configured to turn on the first switch; and during a sensing state after the pre-charge state, the sense amplifier is configured to turn off the second switch.
11. The circuit of claim 9 , wherein the output stage comprises: a first transistor coupled between a first supply node and the second load path terminal of the measuring transistor; and a second transistor coupled between the first supply node and the second load path terminal of the reference transistor, the second transistor having a gate coupled to a gate of the first transistor.
12. The circuit of claim 11 , wherein during the pre-charge state, a current flowing through the second transistor charges a stray capacitance coupled to the first load path terminal of the measuring transistor.
13. The circuit of claim 12 , wherein the output stage further comprises: a third transistor coupled between the first transistor and a second supply terminal; a fourth transistor coupled between the third transistor and the second supply terminal; a fifth transistor coupled between the second transistor and the second supply terminal; and a sixth transistor coupled between the fifth transistor and the second supply terminal, wherein the fifth transistor is coupled to the output terminal.
14. The circuit of claim 13 , wherein the first transistor, second transistor, third transistor, and fifth transistor are PMOS transistors; and the fourth transistor, sixth transistor, measuring transistor, and reference transistor and second switch are NMOS transistor.
15. A method comprising: during a rest state, closing a first switch coupled between a local capacitor and a biasing stage, the local capacitor coupled to a gate of a measuring transistor, the measuring transistor having a first load path terminal coupled to a memory cell and a second load path terminal coupled to an output stage; during a pre-charge state after the rest state, opening the first switch, and closing a second switch coupled between the first load path terminal of the measuring transistor and a first load path terminal of a reference transistor, the first load path terminal of the reference transistor coupled to a reference cell and a second load path terminal of the reference transistor coupled to the output stage; and during a sensing state after the pre-charge state, opening the second switch, and generating an output signal in an output terminal via the output stage based on a state of the memory cell.
16. The method of claim 15 , wherein the memory cell comprises a floating gate MOS transistor.
17. The method of claim 15 , wherein the local capacitor is coupled in series with a local resistor.
18. The method of claim 15 , further comprising during the pre-charge state, charging a stray capacitance coupled to the first load path terminal of the measuring transistor with current flowing through the reference transistor.
19. The method of claim 15 , wherein the output stage comprises: a first transistor coupled between a first supply node and the second load path terminal of the measuring transistor; and a second transistor coupled between the first supply node and the second load path terminal of the reference transistor, the second transistor having a gate coupled to a gate of the first transistor.
20. The method of claim 19 , further comprising during the pre-charge state, charging a stray capacitance coupled to the first load path terminal of the measuring transistor with current flowing through the second transistor.
21. The method of claim 19 , wherein the output stage further comprises: a third transistor coupled between the first transistor and a second supply terminal; a fourth transistor coupled between the third transistor and the second supply terminal; a fifth transistor coupled between the second transistor and the second supply terminal; and a sixth transistor coupled between the fifth transistor and the second supply terminal, wherein the fifth transistor is coupled to the output terminal.
22. The method of claim 21 , further comprising during the pre-charge state, providing a low voltage to a gate of the fourth and sixth transistors; and during the sensing state, providing a high voltage to the gate of the fourth and sixth transistors.
23. The method of claim 22 , wherein the high voltage is between 0.2 V and 0.5 V.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
June 12, 2017
May 21, 2019
Browse 5M+ US patents with plain-English claim translations and AI-generated analysis.