Disclosed are a memory device, including: a memory block including a plurality of cell strings; a peripheral circuit configured to set voltages for a program operation of selected memory cells in the cell strings, and program the selected memory cells by using the set voltages; and a control circuit configured to control the peripheral circuit so that the selected memory cells are programmed in response to a program command, and increase a channel voltage of non-selected cell strings including non-selected memory cells while the selected memory cells are programmed, and an operating method thereof.
Legal claims defining the scope of protection, as filed with the USPTO.
1. An operating method of a memory device, comprising: comparing a pre-set program operation condition with a program operation condition; maintaining a channel voltage of non-selected cell strings with a set-up level when the program operation condition is lower than the pre-set program operation condition as a result of the comparison; increasing the channel voltage when the program operation condition is equal to or higher than the pre-set program operation condition; and programming selected memory cells included in selected cell strings based on one of the maintained channel voltage and the increased channel voltage.
2. The operating method of claim 1 , wherein the program operation condition includes at least one of a target voltage, a verify voltage, and a program time.
3. The operating method of claim 2 , wherein the target voltage is a voltage for completing a program operation of the selected memory cells, the verify voltage is a voltage for verifying the selected memory cells; and the program time is a time for which the program operation of the selected memory cells is performed.
4. The operating method of claim 1 , wherein the channel voltage is increased through a source line voltage applied to a source line, which is commonly connected to the selected cell strings and the non-selected cell strings, or is increased by a precharge voltage applied to bit lines connected to the selected cell strings and the non-selected cell strings.
5. The operating method of claim 4 , further comprising: when the channel voltage is increased through the source line, increasing a turn-on voltage of source select transistors for transferring a voltage applied to the source line to the selected cell strings and the non-selected cell strings.
6. The operating method of claim 4 , further comprising: when the channel voltage is increased through the bit lines, increasing a turn-on voltage of drain select transistors for transferring a voltage applied to the bit lines to the selected cell strings and the non-selected cell strings.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
October 23, 2018
May 28, 2019
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