Apparatuses and methods for sensing a resistance variable memory cell include circuitry to apply a programming signal to a memory cell in the array, the programming signal associated with programming resistance variable memory cells to a particular data state, and detect a change in resistance of the memory cell to determine if a data state of the memory cell changes from an initial data state to a different data state during application of the programming signal.
Legal claims defining the scope of protection, as filed with the USPTO.
1. An apparatus, comprising: an array of resistance variable memory cells; and circuitry, coupled to the array of resistance variable memory cells, including a comparator to detect a change in resistance of a memory cell, wherein the memory cell is selected by applying a select signal to a word line coupled to the memory cell, by comparing a signal on a bit line coupled to the memory cell when a programming signal is applied to the memory cell to a signal associated with a reference signal applied to the circuitry while the programming signal is applied to the memory cell, wherein a voltage of the reference signal increases as a current of the programming signal increases and wherein the circuitry indicates that a data state of the memory cell is a data state that is different from the data state associated with the programming signal when the signal associated with the memory cell input into the comparator is from a capacitor.
2. The apparatus of claim 1 , wherein a current of the reference signal corresponds to a current of the programming signal applied to the memory cell.
3. The apparatus of claim 1 , wherein the comparator detects change in resistance of the memory cell when the signal on the bit line coupled to the memory cell causes a signal associated with the capacitor to be input into the comparator.
4. The apparatus of claim 3 , wherein the signal on the bit line coupled to the memory cell causes the signal associated with the capacitor to be input into the comparator in response to a drop in resistance of the memory cell.
5. The apparatus of claim 1 , wherein the comparator detects an unchanged resistance of the memory cell when the signal on the bit line coupled to the memory cell and the signal associated with the reference signal are input into the comparator.
6. The apparatus of claim 1 , wherein the circuitry indicates that the data state of the memory cell is a data state associated with the programming signal when the signal on the bit line coupled to the memory cell is input into the comparator.
7. An apparatus, comprising: an array of resistance variable memory cells; and circuitry coupled to the array of resistance variable memory cells and including a comparator, a first diode, a second diode, a first capacitor, and a second capacitor, wherein the circuitry is configured to: determine a memory cell, wherein the memory cell is selected by applying a select signal to a word line coupled to the memory cell, is programmed to a particular data state responsive to a programming signal being applied to the memory cell while a reference signal is applied to the circuitry and the comparator receiving a first signal associated with the reference signal and a second signal on a bit line coupled to the memory cell, wherein a voltage of the reference signal increases as a current of the programming signal increases; and determine the memory cell is programmed to another data state responsive to the programming signal being applied to the memory cell while the reference signal is applied to the circuitry and the comparator receiving a third signal associated with the first capacitor and the first signal associated with the reference signal.
8. The apparatus of claim 7 , wherein the first capacitor is configured to discharge in response to the first diode not passing the second signal on the bit line coupled to the memory cell.
9. The apparatus of claim 7 , wherein the first diode is configured to not pass the second signal on the bit line coupled to the memory cell in response to a drop in voltage of the second signal associated with the memory cell.
10. The apparatus of claim 7 , wherein the first capacitor and the second capacitor are charged prior to applying the programming signal to the memory cell.
11. The apparatus of claim 7 , wherein the first capacitor and the second capacitor are charged with signals having a common voltage.
12. The apparatus of claim 7 , wherein the comparator outputs a fourth signal to a latch that indicates whether a resistance of the memory cell has changed.
13. The apparatus of claim 12 , wherein the latch outputs a fifth signal that indicates whether a data state of the memory cell has changed.
14. A method, comprising: applying a programming signal to a memory cell while applying a reference signal to circuitry configured to determine a data state of the memory cell, wherein a voltage of the reference signal increases as a current of the programming signal increases and wherein the memory cell is selected by applying a select signal to a word line coupled to the memory cell; applying a first signal on a bit line coupled to the memory cell to a comparator; applying a second signal associated with the reference signal to the comparator; determining that a resistance of the memory cell remained the same while applying the programming signal in response to the comparator detecting that that first signal matches the second signal; and determining that the resistance of the memory cell changed while applying the programming signal in response to the comparator detecting that that first signal is different than the second signal.
15. The method of claim 14 , wherein determining the resistance of the memory cell remained the same while applying the programming signal includes passing the first signal on the bit line coupled to the memory cell through a first diode to the comparator.
16. The method of claim 14 , wherein determining the resistance of the memory cell changed while applying the programming signal including passing a signal from a capacitor to the comparator.
17. The method of claim 14 , further including determining the memory cell is programmed to a state associated with the programming signal in response to the comparator detecting that that first signal matches the second signal.
18. The method of claim 14 , further determining the memory cell is programmed to another state that is different than the state associated with the programming signal in response to the comparator detecting that that first signal is different than the second signal.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
June 28, 2017
July 30, 2019
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