Dynamically switching cores on a heterogeneous multi-core processing system may be performed by executing program code on a first processing core. Power up of a second processing core may be signaled. A first performance metric of the first processing core executing the program code may be collected. When the first performance metric is better than a previously determined core performance metric, power down of the second processing core may be signaled and execution of the program code may be continued on the first processing core. When the first performance metric is not better than the previously determined core performance metric, execution of the program code may be switched from the first processing core to the second processing core.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A multi-core processing system comprising: a system memory; a first processor core of a first type to execute program code; a second processor core of a second type different from the first type; and a code distribution module to (i) determine, while the first processor core executes the program code, one or more performance metrics of the first processor core and a performance of execution of the second processor core indicative of execution of the same program code by the second processor core, wherein to determine the performance of execution of the second processor core comprises to apply the one or more performance metrics of the first processor core as an input to a prediction function, and (ii) switch execution of the program code from the first processor core to the second processor core in response to a determination that the one or more performance metrics of the second processor core are better than the one or more performance metrics of the first processor core or continue execution of the program code with the first processor core in response to a determination that the one or more performance metrics of the second processor core are not better than the one or more performance metrics of the first processor core.
2. The multi-core processing system of claim 1 , wherein the one or more performance metrics include an amount of power consumed during execution of a code region.
3. The multi-core processing system of claim 1 , wherein the code distribution module is further to power down the first processor core in response to a switch in execution of the program code from the first processor core to the second processor core.
4. The multi-core processing system of claim 1 , wherein the first processor core is an in-order processor core and the second processor core is an out-of-order processor core.
5. The multi-core processing system of claim 1 , wherein the second processor core is an in-order processor core and the first processor core is an out-of-order processor core.
6. The multi-core processing system of claim 1 , further comprising an integrated circuit that includes the first processor core, the second processor core, and the code distribution module.
7. The multi-core processing system of claim 6 , wherein the integrated circuit further comprises a memory controller to manage a memory shared by the first processor core and the second processor core.
8. The multi-core processing system of claim 1 , further comprising a graphics processor.
9. The multi-core processing system of claim 1 , further comprising a network circuitry.
10. The multi-core processing system of claim 1 , wherein the system memory comprises random access memory (RAM).
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
January 2, 2016
October 8, 2019
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