Increasing error rate detection through distribution of read current load

Methods and devices for increasing error detection rate while avoiding excessive power distribution network noise are provided. In one method, memory reads of configuration memory of a first group of sectors of a programmable logic device are performed. The memory reads start at a first start time within a first memory read period. The first memory read period includes an amount of time involved to perform one of the memory reads. The method also includes performing memory reads of configuration memory of a second group of sectors of the programmable logic device. The memory reads of the configuration memory of the second group of sectors start at a second start time within the first memory read period. The second start time is different from the first start time. By offsetting the start times of memory reads, power distribution noise may be reduced.