Semiconductor package

1. A semiconductor package, comprising: a dielectric layer having a first surface and a second surface opposite to the first surface; and a conductive post disposed in the dielectric layer, the conductive post comprising a first portion and a second portion disposed above the first portion, the second portion of the conductive post being recessed from the second surface of the dielectric layer, wherein the second surface of the dielectric layer has an arithmetic average surface roughness (Ra) value, and wherein the Ra value is greater than approximately 450 nanometers (nm).

2. The semiconductor package of claim 1 , wherein the dielectric layer defines a tapered opening adjacent to the second portion of the conductive post.

3. The semiconductor package of claim 2 , further comprising a first patterned conductive layer extended into the tapered opening and in contact with the second portion of the conductive post.

4. The semiconductor package of claim 3 , wherein the first patterned conductive layer comprises a first sublayer and a second sublayer, the first sublayer layer disposed between the second sublayer and the second portion of the conductive post.

5. The semiconductor package of claim 3 , further comprising a second patterned conductive layer electrically connected to the first portion of the conductive post.

6. The semiconductor package of claim 5 , wherein the second patterned conductive layer comprises a sublayer, the sublayer of the second patterned conductive layer including titanium (Ti).

7. The semiconductor package of claim 5 , further comprising a first electrical component, the first electrical component embedded in the dielectric layer and disposed between the first patterned conductive layer and the second patterned conductive layer.

8. The semiconductor package of claim 1 , wherein the dielectric layer includes a molding material.

9. The semiconductor package of claim 1 , wherein the Ra value is less than approximately 12 micrometers (μm).

10. The semiconductor package of claim 9 , wherein the dielectric layer has a sidewall that defines a tapered opening adjacent to the second portion of the conductive post, wherein the sidewall of the dielectric layer has an Ra value substantially the same as the Ra value of the second surface of the dielectric layer.

11. The semiconductor package of claim 1 , wherein the Ra value is in a range from approximately 3 μm to approximately 10 μm.

12. A semiconductor package, comprising: a dielectric layer having a first surface and a second surface opposite to the first surface, wherein the second surface of the dielectric layer has an arithmetic average surface roughness (Ra) value, and wherein the Ra value is greater than approximately 450 nanometers (nm); a conductive post disposed in the dielectric layer, wherein the dielectric layer defines a tapered opening adjacent to the conductive post; and a patterned conductive layer extending into the tapered opening and in contact with the conductive post.

13. The semiconductor package of claim 12 , wherein the patterned conductive layer comprises a first sublayer and a second sublayer, the first sublayer layer disposed between the second sublayer and the conductive post.

14. The semiconductor package of claim 12 , further comprising an electrical component, the electrical component embedded in the dielectric layer.

15. The semiconductor package of claim 12 , wherein the dielectric layer comprises a molding material.

16. The semiconductor package of claim 12 , wherein the Ra value is less than approximately 12 micrometers (μm).

17. The semiconductor package of claim 16 , wherein the dielectric layer has a sidewall that defines the tapered opening adjacent to the conductive post, and the sidewall of the dielectric layer has an Ra value substantially the same as the Ra value of the second surface of the dielectric layer.

18. The semiconductor package of claim 12 , wherein the Ra value is in a range from approximately 3 μm to approximately 10 μm.