Bonding pad structure of a semiconductor device

1. A semiconductor device comprising: a semiconductor chip; a metal electrode formed on a surface of the semiconductor chip; and metal wiring connected to the metal electrode via a bonding part, wherein an outer peripheral of the metal wiring is covered with a metal layer consisting of a metal or an alloy different from a constituent metal of the metal electrode, the bonding part has an alloy region harder than the metal wiring, and the metal layer is formed on an upper surface and a lower surface of at least the metal wiring, and a part of the lower surface contacts the bonding part.

2. The semiconductor device according to claim 1 , wherein the metal layer is an alloy essentially consisting of Zn and Al, and the metal wiring is one of Ag, Al, Au, Cu, and an alloy essentially consisting of one of Ag, Al, Au, and Cu.

3. The semiconductor device according to claim 1 , wherein the metal layer is an alloy essentially consisting of Au, and the metal wiring is one of Al, Cu, and an alloy essentially consisting of Al and Cu.

4. The semiconductor device according to claim 1 , wherein the metal layer is one of Sn and an alloy essentially consisting of Sn, and the metal wiring is one of Ag, Au, Cu, and an alloy essentially consisting of one of Ag, Au, and Cu.

5. The semiconductor device according to claim 1 , wherein a flat region is formed on the metal wiring that is covered by the metal layer, the flat region being positioned at a side opposite from the bonding part, a longitudinal length of the flat region, which is determined in a wiring direction along which the metal wiring extends, is the same as a length of the bonding part, which is determined in the wiring direction.

6. The semiconductor device according to claim 5 , wherein the flat region is shaped while the bonding part is formed by ultrasonic being applied to the metal wiring.

7. A semiconductor device comprising: a semiconductor chip; a metal electrode formed on a surface of the semiconductor chip, the metal electrode being formed of a constituent metal; a metal layer formed on a surface of the metal electrode opposite to the semiconductor chip; and metal wiring connected to the metal layer via a bonding part such that the boding part is disposed on a surface of the metal layer and intervenes between the metal layer and the metal wiring, wherein the metal layer is either made of Sn, or an alloy essentially consisting of Sn, the metal wiring is either made of one of Ag and Cu or an alloy essentially consisting of one of Ag and Cu, the bonding part has an alloy region harder than the metal wiring, defining a first interface that is between the metal layer and the bonding part, the first interface invades the metal layer by penetrating toward the metal layer from the surface of the metal layer, and defining a second interface that is between the bonding part and the metal wiring, the second interface invades the metal wiring by penetrating toward the metal wiring from the surface of the metal layer.

8. The semiconductor device according to claim 7 , wherein a flat region is formed on the metal wiring, the flat region being positioned at a side opposite from the bonding part, a longitudinal length of the flat region, which is determined in a wiring direction along which the metal wiring extends, is substantially the same as a length of the bonding part, which is determined in the wiring direction.

9. The semiconductor device according to claim 8 , wherein the flat region is shaped while the bonding part is formed by ultrasonic being applied to the metal wiring.

10. A semiconductor device comprising: a semiconductor chip; a metal electrode formed on a surface of the semiconductor chip; and metal wiring connected to the metal electrode via a bonding part, wherein an outer peripheral of the metal wiring is covered with a metal layer consisting of a metal or an alloy different from a constituent metal of the metal electrode, the bonding part has an alloy region harder than the metal wiring, the bonding part contacts the metal electrode and the metal wiring, a flat region is formed on the metal wiring that is covered by the metal layer, the flat region being positioned at a side opposite from the bonding part, and a longitudinal length of the flat region, which is determined in a wiring direction along which the metal wiring extends, is the same as a length of the bonding part, which is determined in the wiring direction.

11. The semiconductor device according to claim 10 , wherein the metal layer is an alloy essentially consisting of Zn and Al, and the metal wiring is one of Ag, Al, Au, Cu, and an alloy essentially consisting of one of Ag, Al, Au, and Cu.

12. The semiconductor device according to claim 10 , wherein the metal layer is an alloy essentially consisting of Au, and the metal wiring is one of Al, Cu, and an alloy essentially consisting of Al and Cu.

13. The semiconductor device according to claim 10 , wherein the metal layer is one of Sn and an alloy essentially consisting of Sn, and the metal wiring is one of Ag, Au, Cu, and an alloy essentially consisting of one of Ag, Au, and Cu.

14. The semiconductor device according to claim 10 , wherein the flat region is shaped while the bonding part is formed by ultrasonic being applied to the metal wiring.