Patentable/Patents/US-10484166
US-10484166

Receiver

PublishedNovember 19, 2019
Assigneenot available in USPTO data we have
Inventorsnot available in USPTO data we have
Technical Abstract

A receiver includes: an A/D converter that performs an analog digital conversion of an input signal; an equalizer that equalizes an output from the A/D converter, eliminates inter code interference and obtains a data output; a timing recovery part that generates a recovery clock from the data output of the equalizer; a detector that detects the timing when an input signal varies from a no-signal state and has reached a predetermined threshold; and an initial phase setting part that sets as the initial phase of the recovery clock by the timing recovery part, a timing when the predetermined time has elapsed after the timing detected by the detector.

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Patent Metadata

Filing Date

September 5, 2016

Publication Date

November 19, 2019

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