Disclosed herein is an apparatus that includes a memory cell array, a row hammer refresh circuit configured to generate a row hammer refresh address based on an access history of the memory cell array, a redundancy circuit configured to store a plurality of detective addresses of the memory cell array, and a row pre-decoder configured to skip a refresh operation on the row hammer refresh address when the row hammer refresh address matches any one of the plurality of defective addresses.
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1. An apparatus comprising: a memory cell array; a row hammer refresh circuit configured to generate a row hammer refresh address based on an access history of the memory cell array; a redundancy circuit configured to store a plurality of defective addresses of the memory cell array; and a row pre-decoder configured to skip a refresh operation on the row hammer refresh address when the row hammer refresh address matches any one of the plurality of defective addresses.
Semiconductor memory technology. This invention addresses the problem of row hammer effects in memory cell arrays, which can cause data corruption due to repeated access to adjacent rows. The apparatus includes a memory cell array. A row hammer refresh circuit monitors the access history of the memory cell array and generates a row hammer refresh address. A redundancy circuit stores a list of defective addresses within the memory cell array. A row pre-decoder is configured to prevent a refresh operation from being performed on the generated row hammer refresh address if that address is present in the stored list of defective addresses. This ensures that refresh operations are not unnecessarily performed on known defective rows, potentially mitigating row hammer issues and improving memory reliability.
2. The apparatus of claim 1 , wherein the redundancy circuit is configured to compare the row hammer refresh address with the plurality of defective addresses responsive to a first refresh command, and wherein the row pre-decoder is configured to perform the refresh operation on the row hammer refresh address responsive to a second refresh command when the row hammer refresh address does not match any one of the plurality of defective addresses.
This invention relates to memory systems, specifically addressing the row hammer problem in dynamic random-access memory (DRAM). The row hammer effect occurs when repeated access to adjacent memory rows causes data corruption in nearby rows due to electrical interference. Conventional solutions often involve periodic refresh operations, but these can be inefficient and may inadvertently refresh defective rows, leading to further errors. The apparatus includes a redundancy circuit and a row pre-decoder. The redundancy circuit compares a row hammer refresh address with a stored list of defective addresses when a first refresh command is received. If the refresh address does not match any defective address, the row pre-decoder executes a refresh operation on that address in response to a second refresh command. This ensures that only valid rows are refreshed, preventing unnecessary operations on defective rows and improving memory reliability. The system dynamically checks addresses against a defect list before refreshing, optimizing refresh operations and reducing the risk of data corruption. This approach enhances memory performance and longevity by avoiding refresh operations on known defective rows while maintaining protection against row hammer-induced errors.
3. The apparatus of claim 2 , wherein the memory cell array includes a regular array and a redundant array, and wherein the plurality of defective addresses stored in the redundancy circuit are assigned to the regular array.
The invention relates to memory devices, specifically addressing the issue of defective memory cells in integrated circuits. Memory devices often contain defective cells that must be managed to ensure reliable operation. The invention provides an apparatus with a memory cell array divided into a regular array and a redundant array. The redundant array is used to replace defective cells in the regular array. A redundancy circuit stores addresses of defective cells in the regular array and assigns these addresses to the redundant array, effectively replacing the defective cells with functional ones. This ensures that the memory device operates correctly by isolating and bypassing defective cells. The apparatus may include additional features such as error detection and correction mechanisms to further enhance reliability. The redundant array provides a backup for defective cells, improving the overall yield and performance of the memory device. This approach is particularly useful in high-density memory systems where defects are more likely to occur. The invention ensures that defective cells do not affect the functionality of the memory device, maintaining data integrity and system reliability.
4. The apparatus of claim 3 , wherein the row pre-decoder is configured to perform the refresh operation on the row hammer refresh address when the row hammer refresh address indicates an effective address in the redundant array.
Technical Summary: This invention relates to memory systems, specifically addressing the problem of row hammering in dynamic random-access memory (DRAM). Row hammering occurs when repeated access to adjacent memory rows causes unintended data corruption in neighboring rows due to electrical interference. The invention provides an apparatus to mitigate this issue by performing targeted refresh operations on vulnerable memory rows. The apparatus includes a row pre-decoder that monitors memory access patterns to detect potential row hammering events. When a row hammer refresh address is identified, the pre-decoder checks whether the address corresponds to an effective address in a redundant array—a backup memory region used to replace defective cells. If the address is valid in the redundant array, the pre-decoder initiates a refresh operation to restore the integrity of the affected data. This selective refresh approach reduces unnecessary refresh cycles, improving memory efficiency while preventing data corruption. The system also includes a row hammer detection circuit that tracks access frequencies to adjacent rows and generates refresh addresses when a threshold is exceeded. A redundant array management unit ensures that only valid addresses within the redundant array trigger refresh operations, avoiding redundant refreshes on non-functional or reserved memory regions. This targeted approach enhances reliability and performance in memory systems susceptible to row hammering effects.
5. The apparatus of claim 4 , wherein the row pre-decoder is configured to skip the refresh operation on the row hammer refresh address when the row hammer refresh address indicates an unused address in the redundant array.
Technical Summary: This invention relates to memory systems, specifically addressing the issue of row hammering in dynamic random-access memory (DRAM). Row hammering occurs when repeated access to adjacent memory rows causes data corruption due to electrical interference. Traditional solutions involve periodic refresh operations to mitigate this effect, but these can be inefficient if applied to unused or redundant memory addresses. The apparatus includes a row pre-decoder that intelligently skips refresh operations for specific memory addresses. The pre-decoder checks whether a row hammer refresh address corresponds to an unused address in a redundant array—a backup section of memory used to replace faulty cells. If the address is unused, the refresh operation is skipped, reducing unnecessary power consumption and improving system efficiency. This selective refresh mechanism ensures that only active memory rows receive refresh cycles, optimizing performance without compromising data integrity. The redundant array is a secondary memory block that replaces defective cells in the main memory array. The row pre-decoder interfaces with this redundant array to determine address validity before initiating refresh operations. By avoiding refreshes on unused redundant addresses, the system conserves energy and reduces wear on memory cells. This approach is particularly useful in high-density memory systems where row hammering is a significant reliability concern. The invention enhances memory efficiency by dynamically adapting refresh operations based on actual memory usage.
6. The apparatus of claim 5 , wherein the redundancy circuit includes a plurality of memory sets, each of the memory sets storing a defective address in the regular array and an enable bit that indicates the memory set is enabled or not, and wherein the redundancy circuit is configured to compare the row hammer refresh address with the defective address in each of the memory sets when the row hammer refresh address is directed to the regular array.
This invention relates to memory systems, specifically addressing the problem of row hammering in dynamic random-access memory (DRAM). Row hammering occurs when repeated access to a memory row causes adjacent rows to degrade, leading to data corruption. The invention provides a redundancy circuit to mitigate this issue by identifying and managing defective memory addresses resulting from row hammering. The redundancy circuit includes multiple memory sets, each storing a defective address from the regular memory array and an enable bit indicating whether the memory set is active. When a row hammer refresh address is directed to the regular array, the redundancy circuit compares this address with the defective addresses stored in each memory set. If a match is found, the redundancy circuit can take corrective action, such as redirecting access or triggering a refresh operation to prevent data loss. This proactive approach helps maintain data integrity by dynamically addressing potential row hammering-induced failures. The enable bit allows selective activation or deactivation of individual memory sets, providing flexibility in managing redundancy resources. The system ensures reliable memory operation by continuously monitoring and mitigating the effects of row hammering.
7. The apparatus of claim 6 , wherein each of the memory sets in the redundancy circuit having a different set address, and wherein the redundancy circuit further includes a decoder that converts the row hammer refresh address directed to the redundant array into a row hammer refresh set address, the redundancy circuit being configured to decide that the enable bit assigned to the memory set whose set address matches the row hammer refresh set address is activated or not.
This invention relates to memory systems, specifically addressing row hammer mitigation in semiconductor memory devices. The problem solved is the unintended activation of redundant memory cells due to aggressive row hammer refresh operations, which can lead to data corruption or system failures. The apparatus includes a redundancy circuit with multiple memory sets, each having a unique set address. The redundancy circuit also includes a decoder that converts a row hammer refresh address directed to a redundant array into a corresponding row hammer refresh set address. The redundancy circuit then determines whether to activate an enable bit assigned to a memory set based on whether its set address matches the row hammer refresh set address. This ensures that only the relevant memory set is activated during row hammer refresh operations, preventing unintended access to redundant memory cells. The redundancy circuit is designed to selectively enable or disable memory sets in response to row hammer refresh commands, improving reliability by avoiding false activations. The decoder ensures proper address translation, while the enable bit mechanism provides fine-grained control over memory set activation. This approach enhances the robustness of memory systems by mitigating row hammer-induced errors while maintaining efficient redundancy management.
8. The apparatus of claim 1 , further comprising a refresh counter configured to update a refresh address responsive to a refresh command, wherein the row hammer refresh circuit is configured to stop updating the refresh address in the refresh counter until a row hammer refresh operation is completed.
The invention relates to memory systems, specifically addressing the row hammer effect in dynamic random-access memory (DRAM). The row hammer effect occurs when repeated access to adjacent memory rows causes data corruption in nearby rows due to electrical interference. To mitigate this, the invention includes a refresh counter that updates a refresh address in response to a refresh command. The refresh counter is integrated with a row hammer refresh circuit, which temporarily halts the refresh address updates until a row hammer refresh operation is completed. This ensures that the refresh process prioritizes addressing potential row hammer vulnerabilities before resuming normal refresh operations. The system prevents data corruption by systematically refreshing rows at risk of interference, improving memory reliability. The refresh counter and row hammer refresh circuit work together to dynamically manage refresh operations, ensuring that critical refreshes are not interrupted. This approach enhances the stability of DRAM by mitigating the row hammer effect while maintaining efficient memory performance.
9. An apparatus comprising: a memory cell array; a row hammer refresh circuit configured to generate a row hammer refresh address based on an access history of the memory cell array; a latch circuit configured to latch the row hammer refresh address responsive to a first occurrence of a refresh command; and a row pre-decoder configured to perform a refresh operation on the row hammer refresh address responsive to a second occurrence of the refresh command.
This invention relates to memory systems, specifically addressing the row hammer problem in dynamic random-access memory (DRAM). The row hammer effect occurs when repeated access to adjacent memory rows causes data corruption in nearby rows due to electrical interference. The invention provides a solution to mitigate this issue by implementing a targeted refresh mechanism. The apparatus includes a memory cell array where data is stored. A row hammer refresh circuit monitors access patterns to the memory cell array and generates a row hammer refresh address based on the access history, identifying rows that are at risk of corruption. A latch circuit temporarily stores this refresh address when a refresh command is first received. A row pre-decoder then performs a refresh operation on the identified row hammer refresh address when a subsequent refresh command is received. This two-step process ensures that the refresh operation is performed only on the most vulnerable rows, reducing unnecessary refresh cycles and improving memory efficiency while preventing data corruption. The system dynamically adapts to access patterns, prioritizing rows that are frequently accessed and adjacent to other frequently accessed rows, thereby mitigating the row hammer effect without requiring extensive additional hardware or complex algorithms. The invention enhances memory reliability and performance by selectively refreshing only the rows at risk of corruption.
10. The apparatus of claim 9 , wherein the memory cell array includes a regular array and a redundant array, wherein the regular array includes a normal memory cell and a defective memory cell, and wherein the row pre-decoder is configured to perform the refresh operation on the row hammer refresh address when the row hammer refresh address is directed to the normal memory cell in the regular array.
The apparatus is a memory system designed to mitigate row hammer effects in semiconductor memory devices. Row hammering occurs when repeated access to adjacent memory rows causes unintended data corruption in neighboring cells due to electrical interference. This system includes a memory cell array divided into a regular array and a redundant array. The regular array contains both normal and defective memory cells, while the redundant array is used to replace defective cells. A row pre-decoder is configured to perform refresh operations on specific addresses, known as row hammer refresh addresses, to prevent data corruption. The pre-decoder ensures that refresh operations are only performed on normal memory cells within the regular array, avoiding unnecessary refreshes on defective cells or redundant array cells. This selective refresh mechanism improves memory reliability and efficiency by focusing refresh operations on cells most susceptible to row hammering while bypassing defective or redundant cells. The system enhances data integrity and extends the lifespan of memory devices by dynamically addressing row hammer vulnerabilities.
11. The apparatus of claim 10 , wherein the row pre-decoder is configured to skip the refresh operation on the row hammer refresh address when the row hammer refresh address is directed to the defective memory cell in the regular array.
The apparatus relates to memory systems, specifically addressing the issue of row hammering in dynamic random-access memory (DRAM). Row hammering occurs when repeated access to adjacent memory rows causes unintended data corruption in nearby rows due to electrical interference. Traditional solutions involve periodic refresh operations to mitigate this effect, but these can be inefficient, especially when applied to defective memory cells that do not require refresh. The apparatus includes a row pre-decoder that selectively skips refresh operations for defective memory cells in the regular array. The row pre-decoder identifies a row hammer refresh address, which is a memory row flagged for refresh due to potential row hammering effects. If this address corresponds to a defective memory cell, the pre-decoder bypasses the refresh operation, conserving power and improving system efficiency. The defective memory cells are pre-identified and stored in a defect map or similar tracking mechanism. This selective refresh approach ensures that only functional memory cells undergo refresh operations, reducing unnecessary overhead while maintaining data integrity. The apparatus integrates with existing memory controllers and DRAM modules, enhancing reliability without significant hardware modifications.
12. The apparatus of claim 11 , wherein the redundant array includes a used memory cell substituting the defective memory cell in the regular array and an unused memory cell, and wherein the row pre-decoder is configured to perform the refresh operation on the row hammer refresh address when the row hammer refresh address is directed to the used memory cell in the redundant array.
This invention relates to memory systems, specifically addressing the issue of row hammering in dynamic random-access memory (DRAM). Row hammering occurs when repeated access to a specific memory row causes adjacent rows to degrade, leading to data corruption. The invention provides a solution by implementing a redundant array to replace defective memory cells and a row pre-decoder to manage refresh operations. The apparatus includes a regular memory array and a redundant array. The redundant array contains a used memory cell that substitutes for a defective cell in the regular array and an unused memory cell. A row pre-decoder is configured to perform refresh operations on a row hammer refresh address when that address targets the used memory cell in the redundant array. This ensures that the redundant array is properly maintained, preventing data loss due to row hammering. The pre-decoder also handles address decoding and refresh operations, optimizing memory reliability without requiring additional external intervention. The system dynamically manages defective cells and refreshes critical rows, improving overall memory stability and longevity.
13. The apparatus of claim 12 , wherein the row pre-decoder is configured to skip the refresh operation on the row hammer refresh address when the row hammer refresh address is directed to the unused memory cell in the redundant array.
Technical Summary: The invention relates to memory systems, specifically addressing the issue of row hammering in dynamic random-access memory (DRAM). Row hammering occurs when repeated access to adjacent memory rows causes unintended data corruption in neighboring rows due to electrical interference. Traditional solutions involve periodic refresh operations to mitigate this effect, but these can be inefficient, especially when targeting unused or redundant memory cells. The apparatus includes a row pre-decoder that optimizes refresh operations by selectively skipping refresh cycles for memory addresses directed to unused cells in a redundant array. The redundant array is a backup section of memory used to replace defective cells, and refreshing these unused cells is unnecessary. By detecting and bypassing such addresses, the system reduces unnecessary refresh operations, conserves power, and improves overall memory efficiency without compromising data integrity. The row pre-decoder works in conjunction with a row hammer detection mechanism that identifies potential row hammering events and generates refresh addresses accordingly. The pre-decoder then filters these addresses, ensuring only valid, active memory cells are refreshed. This selective approach enhances performance and reliability in memory systems prone to row hammering effects.
14. The apparatus of claim 9 , further comprising a refresh counter configured to update a refresh address responsive to the refresh command, wherein the row hammer refresh circuit is configured to stop updating the refresh address in the refresh counter until a row hammer refresh operation is completed.
The invention relates to memory systems, specifically addressing the issue of row hammering in dynamic random-access memory (DRAM). Row hammering occurs when repeated access to a memory row causes unintended data corruption in adjacent rows due to electrical interference. This can lead to system instability or data loss. The apparatus includes a refresh counter that updates a refresh address in response to a refresh command. The refresh counter is part of a row hammer refresh circuit designed to mitigate row hammering effects. The circuit is configured to halt updates to the refresh address in the refresh counter until a row hammer refresh operation is fully completed. This ensures that the refresh process is not interrupted, preventing partial or incomplete refreshes that could leave memory rows vulnerable to corruption. The apparatus may also include a refresh address generator that provides the refresh address to the refresh counter, and a refresh control circuit that manages the refresh operations. The row hammer refresh circuit may further include a row hammer detection circuit that identifies potential row hammering events, triggering the refresh operations as needed. By pausing address updates during refresh, the system ensures reliable and complete mitigation of row hammering effects.
15. The apparatus of claim 14 , wherein the latch circuit is configured to latch the refresh address responsive to the second occurrence of the refresh command; and wherein the row pre-decoder is configured to perform the refresh operation on the refresh address responsive to a third occurrence of the refresh command.
This invention relates to memory systems, specifically to a method and apparatus for managing refresh operations in memory devices. The problem addressed is the need to efficiently handle refresh commands in memory systems, particularly in scenarios where multiple refresh commands are received in quick succession, to prevent data loss and ensure reliable operation. The apparatus includes a latch circuit and a row pre-decoder. The latch circuit is configured to capture or hold a refresh address when a second refresh command is received. This ensures that the refresh address is retained for subsequent processing. The row pre-decoder is then configured to perform the actual refresh operation on the latched refresh address when a third refresh command is received. This staggered approach allows the memory system to handle multiple refresh commands without losing or corrupting data, improving reliability and performance. The invention ensures that refresh operations are executed in a controlled manner, even when multiple refresh commands are issued in rapid succession. This is particularly useful in high-speed memory systems where timely and accurate refresh operations are critical to maintaining data integrity. The apparatus may be part of a larger memory controller or integrated within a memory device itself.
16. An apparatus comprising: a memory cell array including a regular array and a redundant array; a redundancy circuit including a plurality of memory sets each storing a defective address in the regular array and an enable bit that indicates the memory set is enabled or not, each of the memory sets having a different set address; a refresh counter configured to update a refresh address responsive to a refresh command; and a row pre-decoder configured to perform a refresh operation on the refresh address when the refresh address is directed to the regular array and does not match the defective address stored in any of the memory sets in the redundancy circuit, and configured to skip the refresh operation on the refresh address when the refresh address is directed to the redundant array and when the memory set corresponding to the refresh address is not enabled.
This invention relates to memory systems, specifically addressing the challenge of efficiently managing refresh operations in memory devices with redundant arrays. The apparatus includes a memory cell array divided into a regular array and a redundant array, used to replace defective cells in the regular array. A redundancy circuit stores defective addresses from the regular array along with enable bits indicating whether each memory set is active. Each memory set has a unique set address. A refresh counter generates refresh addresses in response to refresh commands. A row pre-decoder controls the refresh process by comparing the refresh address against the defective addresses stored in the redundancy circuit. If the refresh address targets the regular array and does not match any defective address, the refresh operation proceeds. If the refresh address targets the redundant array and the corresponding memory set is not enabled, the refresh operation is skipped. This ensures that only valid memory cells are refreshed, improving efficiency and reliability in memory systems with redundancy features. The system optimizes refresh operations by avoiding unnecessary refresh cycles on redundant or disabled memory sets, reducing power consumption and wear on the memory device.
17. The apparatus of claim 16 , wherein the row pre-decoder is configured to skip the refresh operation on the refresh address when the refresh address is directed to the regular array and matches the defective address stored in any of the memory sets in the redundancy circuit.
The invention relates to memory systems, specifically addressing the issue of inefficient refresh operations in memory arrays containing defective cells. In memory systems, periodic refresh operations are required to maintain data integrity, but these operations consume power and time. The problem arises when refresh operations are performed on defective memory cells, which are typically replaced by redundant cells in a redundancy circuit. Performing refresh operations on defective cells is unnecessary and wastes resources. The apparatus includes a row pre-decoder that optimizes refresh operations by skipping them for defective addresses. The row pre-decoder checks whether a refresh address is directed to the regular memory array and compares it against defective addresses stored in the redundancy circuit. If a match is found, the refresh operation for that address is skipped, improving efficiency. The redundancy circuit contains multiple memory sets, each storing defective addresses that have been replaced by redundant cells. The row pre-decoder interacts with this circuit to determine whether a refresh operation should proceed or be skipped. This selective skipping reduces unnecessary refresh cycles, conserving power and improving overall memory performance. The solution is particularly useful in systems where power efficiency and performance are critical, such as mobile devices and embedded systems.
18. The apparatus of claim 17 , wherein the row pre-decoder is configured to perform the refresh operation on the refresh address when the refresh address is directed to the redundant array and when the memory set corresponding to the refresh address is enabled.
A memory apparatus includes a redundant array for repairing defective memory cells and a row pre-decoder that controls refresh operations. The row pre-decoder selectively performs refresh operations on a refresh address when the address targets the redundant array and when the corresponding memory set is enabled. This ensures that only valid memory cells in the redundant array are refreshed, improving efficiency and reliability. The apparatus may include multiple memory sets, each with its own enable signal, allowing selective activation of specific memory sets. The row pre-decoder checks the refresh address against the redundant array's address range and verifies the memory set's enable status before executing the refresh operation. This prevents unnecessary refresh cycles on disabled memory sets or non-redundant addresses, reducing power consumption and wear. The system may also include address decoding logic to determine whether the refresh address falls within the redundant array's range. The apparatus is particularly useful in memory systems requiring high reliability and efficient refresh management, such as embedded memory in processors or standalone memory chips.
19. The apparatus of claim 18 , further comprising: a row hammer refresh circuit configured to generate a row hammer refresh address based on an access history of the memory cell array; and a selector configured to supply one of the refresh address supplied from the refresh counter and the row hammer refresh address supplied from the row hammer refresh circuit to the redundancy circuit.
A memory apparatus includes a memory cell array and a redundancy circuit that replaces defective memory cells with redundant memory cells. The apparatus further includes a refresh counter that generates a periodic refresh address to refresh memory cells in the array. To address the row hammer problem, where repeated access to adjacent rows can cause data corruption, the apparatus includes a row hammer refresh circuit. This circuit monitors access history to the memory cell array and generates a row hammer refresh address for rows that have been accessed frequently. A selector then determines whether to supply the periodic refresh address from the refresh counter or the row hammer refresh address from the row hammer refresh circuit to the redundancy circuit. This ensures that both regular refresh operations and targeted row hammer mitigation are performed, improving memory reliability. The redundancy circuit uses the selected address to refresh the appropriate memory cells, including any redundant cells that have replaced defective ones. This approach prevents data loss due to row hammer effects while maintaining standard refresh operations.
20. The apparatus of claim 19 , wherein the row hammer refresh circuit is configured to stop updating the refresh address in the refresh counter until a row hammer refresh operation is completed.
The apparatus relates to memory systems, specifically addressing the issue of row hammering in dynamic random-access memory (DRAM). Row hammering occurs when repeated access to adjacent memory rows causes unintended data corruption in neighboring rows due to electrical interference. To mitigate this, the apparatus includes a row hammer refresh circuit designed to perform targeted refresh operations on potentially affected rows. The row hammer refresh circuit monitors memory access patterns to detect potential row hammer events. When such an event is identified, the circuit initiates a refresh operation to restore the integrity of the affected rows. A refresh counter is used to track the addresses of rows that require refreshing. The circuit is configured to halt updates to the refresh address in the counter until the current row hammer refresh operation is fully completed. This ensures that the refresh process is not interrupted, preventing partial or incomplete refreshes that could leave data vulnerable to corruption. The apparatus may also include additional components, such as a memory controller and a memory array, to facilitate the detection and mitigation of row hammering. The overall goal is to enhance memory reliability by systematically addressing row hammering without disrupting normal memory operations.
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August 14, 2018
November 26, 2019
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