A thin film transistor (TFT), a method of manufacturing the TFT, and a display apparatus including the TFT, the TFT including a substrate; a semiconductor layer on the substrate, the semiconductor layer including a channel region, a lightly doped drain (LDD) region, a source region, and a drain region; a gate insulating layer covering the semiconductor layer; a gate electrode overlapping with the channel region such that the gate insulating layer is interposed between the gate electrode and the channel region; and an organic side wall layer on a side surface of the gate electrode, wherein the organic side wall layer includes a silsesquioxane resin.
Legal claims defining the scope of protection. Each claim is shown in both the original legal language and a plain English translation.
1. A thin film transistor, comprising: a substrate; a semiconductor layer on the substrate, the semiconductor layer including a channel region, a lightly doped drain (LDD) region, a source region, and a drain region; a gate insulating layer covering the semiconductor layer; a gate electrode overlapping with the channel region such that the gate insulating layer is interposed between the gate electrode and the channel region; and an organic side wall layer on a side surface of the gate electrode, wherein the organic side wall layer includes a silsesquioxane resin wherein: the source region and the drain region include a dopant, and the organic side wall layer further includes a material that is the same as the dopant included in the source region and the drain region.
Technology Domain: Semiconductor Devices, specifically Thin Film Transistors (TFTs). Problem: Improving the performance and reliability of thin film transistors, particularly by reducing leakage current and enhancing the effectiveness of doping in source and drain regions. Invention Summary: This invention describes a thin film transistor (TFT) fabricated on a substrate. The TFT includes a semiconductor layer with distinct regions: a channel region, a lightly doped drain (LDD) region, a source region, and a drain region. A gate insulating layer is positioned over the semiconductor layer, and a gate electrode is situated above the channel region, separated by the gate insulating layer. A key feature is an organic side wall layer applied to the side surface of the gate electrode. This organic side wall layer is composed of a silsesquioxane resin. Crucially, the source and drain regions are doped with a specific dopant. The organic side wall layer itself contains this same dopant material. This integration of the dopant within the organic side wall is intended to enhance the doping profile and performance of the source and drain regions.
2. The thin film transistor as claimed in claim 1 , wherein: the LDD region is at opposite sides of the channel region, and the organic side wall layer overlies the LDD region.
A thin film transistor (TFT) is a semiconductor device used in displays and other electronic applications. A common challenge in TFT design is balancing performance and reliability, particularly in preventing leakage current and ensuring stable operation. This invention addresses these issues by incorporating a lightly doped drain (LDD) region and an organic side wall layer in a specific configuration. The TFT includes a channel region, source and drain regions, and an LDD region positioned at both sides of the channel region. The LDD region helps reduce leakage current by gradually transitioning the electric field between the channel and drain. An organic side wall layer is formed over the LDD region, providing additional structural and electrical benefits. The organic material may act as a passivation layer, protecting the LDD region from contamination or damage while also potentially improving device stability. The side wall layer may also assist in defining the LDD region during fabrication, ensuring precise alignment and consistent performance. This configuration enhances the TFT's reliability by minimizing leakage and improving durability, making it suitable for high-performance applications such as advanced displays and integrated circuits. The use of an organic side wall layer offers flexibility in material selection and processing, allowing for optimized device characteristics.
3. The thin film transistor as claimed in claim 1 , wherein the organic side wall layer extends to an upper surface of the gate electrode.
Technical Summary: This invention relates to thin film transistors (TFTs) with improved structural integrity and performance. The problem addressed is the susceptibility of organic TFTs to degradation due to environmental factors and poor electrical contact between components. The solution involves an organic side wall layer that enhances structural stability and electrical connectivity. The TFT includes a substrate, a gate electrode, a gate insulating layer, a semiconductor layer, a source electrode, and a drain electrode. The organic side wall layer is formed adjacent to the gate electrode and extends to the upper surface of the gate electrode. This layer provides a protective barrier and ensures reliable electrical contact between the gate electrode and other components. The organic side wall layer is made from an organic material that is compatible with the semiconductor layer, ensuring consistent performance and longevity. The organic side wall layer's extension to the upper surface of the gate electrode ensures that the gate electrode is fully encapsulated, preventing exposure to external contaminants and reducing the risk of electrical short circuits. This design also improves the uniformity of the electric field distribution within the TFT, leading to better device performance and reliability. The organic material used for the side wall layer is selected to have high chemical stability and low leakage current, further enhancing the TFT's durability and efficiency. This invention is particularly useful in flexible electronics, displays, and other applications where TFTs are exposed to harsh environmental conditions. The organic side wall layer provides a robust solution to the challenges of organic TFT degradation, ensuring long-term stability and performance
4. The thin film transistor as claimed in claim 3 , wherein a thickness of a portion of the organic side wall layer at the upper surface of the gate electrode is smaller than a thickness of a portion of the organic side wall layer at the gate insulating layer.
This invention relates to thin film transistors (TFTs) with an organic side wall layer, addressing issues such as uniformity and performance in semiconductor devices. The TFT includes a gate electrode, a gate insulating layer, and an organic side wall layer formed adjacent to the gate electrode. The organic side wall layer has varying thickness, where the portion at the upper surface of the gate electrode is thinner than the portion at the gate insulating layer. This design improves device reliability and electrical characteristics by optimizing the side wall structure. The organic side wall layer may be formed using a material such as a polymer or organic dielectric, and its thickness variation is controlled during deposition or etching processes. The TFT may be part of a larger semiconductor device, such as a display panel or integrated circuit, where precise control of the side wall profile is critical for performance. The invention ensures consistent electrical properties and reduces defects by preventing excessive material buildup or uneven etching near the gate electrode. The organic side wall layer also helps in defining the channel region and improving insulation between the gate and other conductive layers. This structure is particularly useful in organic or flexible electronics where precise patterning of organic materials is challenging.
5. A method of manufacturing a thin film transistor, the method comprising: forming a semiconductor layer on a substrate; forming a gate insulating layer on the substrate to cover the semiconductor layer; forming a gate electrode on the gate insulating layer to partially overlap with the semiconductor layer; injecting a first dopant into the semiconductor layer by using the gate electrode as a mask; forming an organic side wall layer surrounding side surfaces of the gate electrode; and injecting a second dopant into the semiconductor layer by using the gate electrode and the organic side wall layer as a mask, wherein the organic side wall layer includes a silsesquioxane resin wherein an inclination of the organic side wall layer is adjusted according to a content of the silsesquioxane resin.
This invention relates to a method for manufacturing a thin film transistor (TFT), addressing challenges in precise doping of semiconductor layers to improve device performance. The method involves forming a semiconductor layer on a substrate, followed by a gate insulating layer that covers the semiconductor. A gate electrode is then formed on the gate insulating layer, partially overlapping the semiconductor layer. A first dopant is injected into the semiconductor layer using the gate electrode as a mask, creating a doped region aligned with the gate electrode. An organic side wall layer is formed around the side surfaces of the gate electrode, using a silsesquioxane resin. The content of the silsesquioxane resin in the organic side wall layer is adjusted to control its inclination, which affects the doping profile. A second dopant is then injected into the semiconductor layer, using both the gate electrode and the organic side wall layer as a mask. This two-step doping process, combined with the tunable organic side wall layer, enables precise control over the doping regions, enhancing the electrical characteristics of the TFT. The silsesquioxane resin-based side wall layer provides flexibility in adjusting the doping profile, improving device uniformity and performance.
6. The method as claimed in claim 5 , wherein forming the organic side wall includes: coating the gate electrode with an organic composition, and baking the organic composition.
Technical Summary: This invention relates to semiconductor device fabrication, specifically to forming organic side walls on gate electrodes in transistor structures. The problem addressed is the need for precise, stable side wall formations to enhance device performance and reliability. The method involves coating a gate electrode with an organic composition, followed by baking the composition to form a solidified organic side wall. The organic composition may include polymers, resins, or other organic materials that can be applied via spin-coating, dip-coating, or other deposition techniques. Baking the composition cures or solidifies the material, creating a durable side wall structure adjacent to the gate electrode. This process is part of a broader method for fabricating a semiconductor device, where the organic side wall serves as a protective or insulating layer. The side wall may also function as a spacer to define critical dimensions in the device, such as the channel length in a transistor. The organic material is selected for its compatibility with subsequent processing steps, such as etching or deposition, and its ability to withstand thermal and chemical conditions during device fabrication. The invention improves upon prior art by using organic materials, which can offer advantages in terms of process flexibility, cost, and performance compared to traditional inorganic side wall materials. The baking step ensures proper adhesion and structural integrity of the side wall, contributing to the overall reliability of the semiconductor device.
7. The method as claimed in claim 6 , wherein the organic composition of includes the silsesquioxane resin in an amount of 1.7 wt % to 5 wt %, based on a weight of the organic composition.
This invention relates to an organic composition containing a silsesquioxane resin, specifically tailored for use in semiconductor manufacturing or related applications. The composition addresses challenges in material formulation, such as achieving desired thermal stability, mechanical properties, or processability, by precisely controlling the silsesquioxane resin content. The organic composition includes the silsesquioxane resin in a concentration range of 1.7% to 5% by weight, relative to the total weight of the composition. This range ensures optimal performance while maintaining compatibility with other components in the formulation. The silsesquioxane resin, a type of organosilicon polymer, contributes to properties like thermal resistance, adhesion, or chemical resistance, making the composition suitable for advanced materials in electronics, coatings, or encapsulation. The specified concentration range balances these properties without compromising processability or cost-effectiveness. The composition may further include additional organic or inorganic additives to enhance functionality, such as fillers, solvents, or cross-linking agents, depending on the intended application. This formulation is particularly useful in applications requiring precise control over material properties, such as in semiconductor packaging, protective coatings, or high-performance adhesives.
8. The method as claimed in claim 5 , wherein a concentration of the first dopant in the semiconductor layer is lower than a concentration of the second dopant in the semiconductor layer.
This invention relates to semiconductor doping techniques, specifically addressing the challenge of optimizing dopant concentration profiles to improve device performance. The method involves forming a semiconductor layer with two distinct dopant regions, where the concentration of a first dopant is lower than that of a second dopant within the same layer. The semiconductor layer is initially doped with the first dopant, followed by selective introduction of the second dopant into specific regions. The second dopant is introduced at a higher concentration than the first, creating a controlled dopant gradient. This gradient enhances electrical properties such as carrier mobility and junction efficiency, which are critical for semiconductor devices like transistors and diodes. The process may include additional steps such as annealing to activate the dopants and stabilize the semiconductor structure. The invention ensures precise dopant distribution, reducing defects and improving device reliability. The method is particularly useful in advanced semiconductor manufacturing where fine-tuned doping profiles are essential for high-performance electronics.
9. The method as claimed in claim 5 , wherein the first dopant and the second dopant are dopants of a same type.
This invention relates to semiconductor manufacturing, specifically to a method of doping semiconductor materials to improve device performance. The problem addressed is achieving precise control over dopant distribution in semiconductor substrates to enhance electrical properties without introducing defects or inconsistencies. The method involves introducing a first dopant and a second dopant into a semiconductor substrate, where both dopants are of the same type (e.g., both n-type or both p-type). The first dopant is implanted at a first depth, and the second dopant is implanted at a second depth, different from the first. This creates a tailored dopant profile that optimizes electrical conductivity and reduces resistance in the semiconductor device. The process may include annealing steps to activate the dopants and repair lattice damage caused by implantation. The method ensures uniform doping across the substrate, minimizing defects and improving device reliability. By using dopants of the same type at different depths, the technique enhances carrier mobility and reduces leakage currents, which is critical for high-performance semiconductor devices. The approach is particularly useful in advanced transistor structures, such as FinFETs or nanowire transistors, where precise doping control is essential for optimal performance.
10. The method as claimed in claim 5 , wherein forming the organic side wall layer further includes forming the layer on an upper surface of the gate electrode.
This invention relates to semiconductor device fabrication, specifically to methods for forming organic side wall layers in transistor structures. The problem addressed is the need for precise and controlled formation of organic side wall layers adjacent to gate electrodes, which is critical for advanced semiconductor devices. The method involves depositing an organic material to form a side wall layer on the side surfaces of a gate electrode structure. Additionally, the organic side wall layer is also formed on the upper surface of the gate electrode. This ensures uniform coverage and protection of the gate electrode during subsequent processing steps. The organic material may be deposited using techniques such as chemical vapor deposition, atomic layer deposition, or spin coating, followed by selective etching or patterning to define the side wall structure. The method is particularly useful in finFET or gate-all-around transistor architectures where precise side wall formation is essential for device performance and reliability. The organic side wall layer may serve as a protective barrier, an etch mask, or a spacer to enable self-aligned processing of source/drain regions or other device features. The invention improves manufacturing yield and device performance by ensuring accurate and consistent side wall formation.
11. The method as claimed in claim 10 , further comprising removing the organic side wall layer from the upper surface of the gate electrode.
Technical Summary: This invention relates to semiconductor fabrication, specifically to methods for forming gate structures in transistors. The problem addressed is the presence of organic side wall layers on gate electrodes, which can interfere with subsequent processing steps or device performance. The method involves removing an organic side wall layer from the upper surface of a gate electrode. This step is performed after forming the gate electrode and its surrounding side walls, which are typically used to define critical dimensions during etching or deposition processes. The organic side wall layer may be deposited as part of a self-aligned contact (SAC) process or other patterning techniques. Removal ensures clean surfaces for subsequent metallization, contact formation, or other integration steps, improving electrical connectivity and reliability. The removal process may involve selective etching, plasma treatment, or other techniques that target the organic material without damaging the gate electrode or underlying structures. This step is particularly important in advanced node technologies where precise control of material interfaces is critical. The method ensures that the gate electrode's upper surface is free of residual organic material, enabling reliable interconnections and optimal device performance.
12. A display apparatus including a thin film transistor, the display apparatus comprising: a planarization layer covering the thin film transistor; a pixel electrode on the planarization layer, the pixel electrode being connected to the thin film transistor; an opposite electrode facing the pixel electrode; and an intermediate layer between the pixel electrode and the opposite electrode, wherein the thin film transistor includes: a semiconductor layer on the substrate, the semiconductor layer including a channel region, a lightly doped drain (LDD) region, a source region, and a drain region; a gate insulating layer covering the semiconductor layer; a gate electrode overlapping with the channel region such that the gate insulating layer is interposed between the gate electrode and the channel region; and an organic side wall layer on a side surface of the gate electrode, wherein the organic side wall layer includes a silsesquioxane resin wherein: the source region and the drain region include a dopant, and the organic side wall layer further includes a material that is the same as the dopant included in the source region and the drain region.
This invention relates to a display apparatus incorporating a thin film transistor (TFT) with an improved structure to enhance performance and reliability. The display apparatus addresses issues such as leakage current and degradation in TFTs by incorporating an organic side wall layer made of silsesquioxane resin on the side surface of the gate electrode. The TFT includes a semiconductor layer with a channel region, a lightly doped drain (LDD) region, a source region, and a drain region, all formed on a substrate. The gate insulating layer covers the semiconductor layer, and the gate electrode overlaps the channel region, with the gate insulating layer separating them. The organic side wall layer, which contains a dopant matching the source and drain regions, helps control doping profiles and reduces parasitic capacitance. The display apparatus further includes a planarization layer covering the TFT, a pixel electrode connected to the TFT, an opposite electrode facing the pixel electrode, and an intermediate layer between them. This configuration improves TFT stability, reduces leakage, and enhances display performance by optimizing the doping and insulating properties of the side wall layer.
13. The display apparatus as claimed in claim 12 , wherein: the LDD region is at opposite sides of the channel region, and the organic side wall layer overlies the LDD region.
A display apparatus includes a thin-film transistor (TFT) with a channel region and a lightly doped drain (LDD) region positioned at opposite sides of the channel region. The TFT further includes an organic side wall layer that overlies the LDD region. The organic side wall layer is formed from an organic material and is positioned adjacent to the LDD region to improve device performance by reducing leakage current and enhancing reliability. The organic side wall layer may also act as a protective barrier, preventing contamination or damage to the LDD region during subsequent processing steps. The TFT structure is integrated into a display panel, such as an organic light-emitting diode (OLED) display, to enhance pixel uniformity and longevity. The organic side wall layer is deposited using a selective deposition process, ensuring precise alignment with the LDD region while maintaining electrical isolation. This configuration improves the stability and efficiency of the TFT, making it suitable for high-resolution and flexible display applications. The organic side wall layer may also be used in conjunction with other insulating or conductive layers to optimize the electrical characteristics of the TFT.
14. The display apparatus as claimed in claim 12 , wherein the organic side wall layer extends to an upper surface of the gate electrode.
A display apparatus includes a substrate with a thin-film transistor (TFT) structure and an organic light-emitting diode (OLED) formed thereon. The TFT structure comprises a gate electrode, a semiconductor layer, and source/drain electrodes. The OLED includes an anode, an organic emission layer, and a cathode. The apparatus further includes an organic side wall layer formed on the substrate, which surrounds the OLED and extends to an upper surface of the gate electrode. This side wall layer is positioned between the anode and the substrate, electrically insulating the anode from the gate electrode while defining the emission area of the OLED. The organic side wall layer is formed from an organic material, such as a photoresist or an insulating polymer, and is patterned to create a precise boundary for the OLED's emission region. The gate electrode, typically made of a conductive material like metal or conductive oxide, is part of the TFT structure and controls the current flow through the semiconductor layer. The organic side wall layer ensures proper electrical isolation and structural support for the OLED, improving device reliability and performance. This configuration is particularly useful in high-resolution display applications where precise control of the emission area is critical.
15. The display apparatus as claimed in claim 14 , wherein a thickness of a portion of the organic side wall layer at the upper surface of the gate electrode is smaller than a thickness of a portion of the organic side wall layer at the gate insulating layer.
This invention relates to display apparatuses, specifically those incorporating organic light-emitting diode (OLED) structures with improved side wall configurations. The problem addressed is the need for precise control of organic layer deposition to enhance device performance and reliability, particularly in OLED displays where organic side walls are used to define active regions. The apparatus includes a substrate with a gate electrode and a gate insulating layer. An organic side wall layer is formed adjacent to the gate electrode, where the thickness of the organic side wall layer at the upper surface of the gate electrode is smaller than its thickness at the gate insulating layer. This tapered or stepped profile ensures better coverage and adhesion of subsequent layers, reducing defects and improving electrical isolation. The organic side wall layer may be formed using photolithography or selective deposition techniques, and its composition can be adjusted to optimize optical and electrical properties. The apparatus may also include additional layers such as a semiconductor layer, source/drain electrodes, and an OLED stack, all integrated with the organic side wall structure to enhance display uniformity and longevity. The invention aims to improve manufacturing yield and device performance by optimizing the organic side wall geometry.
16. The display apparatus as claimed in claim 12 , further comprising a pixel-defining layer exposing a center portion of the pixel electrode and covering an edge of the pixel electrode, the pixel defining layer define pixels.
A display apparatus includes a pixel electrode and a pixel-defining layer. The pixel-defining layer exposes a central portion of the pixel electrode while covering its edge, thereby defining the boundaries of individual pixels. This structure ensures precise pixel formation and prevents electrical shorting between adjacent pixel electrodes. The pixel-defining layer acts as a barrier, isolating each pixel electrode to maintain display uniformity and performance. The apparatus may also include a substrate, a thin-film transistor layer for driving the pixel electrodes, and an organic light-emitting layer positioned above the pixel electrodes. The pixel-defining layer helps control the deposition of the organic light-emitting material, ensuring accurate pixel formation and improving display resolution. This design is particularly useful in organic light-emitting diode (OLED) displays, where precise pixel definition is critical for high-quality imaging. The apparatus may further include additional layers such as an encapsulation layer to protect the organic materials from moisture and air, extending the device's lifespan. The pixel-defining layer's coverage of the pixel electrode edges reduces the risk of defects and enhances manufacturing yield.
17. The display apparatus as claimed in claim 12 , wherein the intermediate layer includes an emission layer.
A display apparatus includes a substrate, a first electrode, a second electrode, and an intermediate layer positioned between the first and second electrodes. The intermediate layer contains an emission layer that emits light when an electric current is applied between the first and second electrodes. The apparatus may also include a pixel circuit connected to the first electrode, where the pixel circuit controls the current flow to the emission layer. The emission layer is typically an organic material that produces light in response to electrical stimulation, forming the basis of an organic light-emitting diode (OLED) display. The intermediate layer may further include additional layers, such as hole injection, hole transport, electron transport, or electron injection layers, to enhance device efficiency and performance. The apparatus is designed to address challenges in display technology, such as improving brightness, color accuracy, and energy efficiency by optimizing the structure and composition of the emission layer and surrounding layers. This configuration allows for high-resolution, self-emissive displays with wide viewing angles and fast response times, suitable for applications in televisions, smartphones, and other electronic devices.
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September 4, 2018
November 26, 2019
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