A thin film transistor (TFT), a method of manufacturing the TFT, and a display apparatus including the TFT, the TFT including a substrate; a semiconductor layer on the substrate, the semiconductor layer including a channel region, a lightly doped drain (LDD) region, a source region, and a drain region; a gate insulating layer covering the semiconductor layer; a gate electrode overlapping with the channel region such that the gate insulating layer is interposed between the gate electrode and the channel region; and an organic side wall layer on a side surface of the gate electrode, wherein the organic side wall layer includes a silsesquioxane resin.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A thin film transistor, comprising: a substrate; a semiconductor layer on the substrate, the semiconductor layer including a channel region, a lightly doped drain (LDD) region, a source region, and a drain region; a gate insulating layer covering the semiconductor layer; a gate electrode overlapping with the channel region such that the gate insulating layer is interposed between the gate electrode and the channel region; and an organic side wall layer on a side surface of the gate electrode, wherein the organic side wall layer includes a silsesquioxane resin wherein: the source region and the drain region include a dopant, and the organic side wall layer further includes a material that is the same as the dopant included in the source region and the drain region.
2. The thin film transistor as claimed in claim 1 , wherein: the LDD region is at opposite sides of the channel region, and the organic side wall layer overlies the LDD region.
3. The thin film transistor as claimed in claim 1 , wherein the organic side wall layer extends to an upper surface of the gate electrode.
4. The thin film transistor as claimed in claim 3 , wherein a thickness of a portion of the organic side wall layer at the upper surface of the gate electrode is smaller than a thickness of a portion of the organic side wall layer at the gate insulating layer.
5. A method of manufacturing a thin film transistor, the method comprising: forming a semiconductor layer on a substrate; forming a gate insulating layer on the substrate to cover the semiconductor layer; forming a gate electrode on the gate insulating layer to partially overlap with the semiconductor layer; injecting a first dopant into the semiconductor layer by using the gate electrode as a mask; forming an organic side wall layer surrounding side surfaces of the gate electrode; and injecting a second dopant into the semiconductor layer by using the gate electrode and the organic side wall layer as a mask, wherein the organic side wall layer includes a silsesquioxane resin wherein an inclination of the organic side wall layer is adjusted according to a content of the silsesquioxane resin.
6. The method as claimed in claim 5 , wherein forming the organic side wall includes: coating the gate electrode with an organic composition, and baking the organic composition.
7. The method as claimed in claim 6 , wherein the organic composition of includes the silsesquioxane resin in an amount of 1.7 wt % to 5 wt %, based on a weight of the organic composition.
8. The method as claimed in claim 5 , wherein a concentration of the first dopant in the semiconductor layer is lower than a concentration of the second dopant in the semiconductor layer.
9. The method as claimed in claim 5 , wherein the first dopant and the second dopant are dopants of a same type.
10. The method as claimed in claim 5 , wherein forming the organic side wall layer further includes forming the layer on an upper surface of the gate electrode.
11. The method as claimed in claim 10 , further comprising removing the organic side wall layer from the upper surface of the gate electrode.
12. A display apparatus including a thin film transistor, the display apparatus comprising: a planarization layer covering the thin film transistor; a pixel electrode on the planarization layer, the pixel electrode being connected to the thin film transistor; an opposite electrode facing the pixel electrode; and an intermediate layer between the pixel electrode and the opposite electrode, wherein the thin film transistor includes: a semiconductor layer on the substrate, the semiconductor layer including a channel region, a lightly doped drain (LDD) region, a source region, and a drain region; a gate insulating layer covering the semiconductor layer; a gate electrode overlapping with the channel region such that the gate insulating layer is interposed between the gate electrode and the channel region; and an organic side wall layer on a side surface of the gate electrode, wherein the organic side wall layer includes a silsesquioxane resin wherein: the source region and the drain region include a dopant, and the organic side wall layer further includes a material that is the same as the dopant included in the source region and the drain region.
13. The display apparatus as claimed in claim 12 , wherein: the LDD region is at opposite sides of the channel region, and the organic side wall layer overlies the LDD region.
14. The display apparatus as claimed in claim 12 , wherein the organic side wall layer extends to an upper surface of the gate electrode.
15. The display apparatus as claimed in claim 14 , wherein a thickness of a portion of the organic side wall layer at the upper surface of the gate electrode is smaller than a thickness of a portion of the organic side wall layer at the gate insulating layer.
16. The display apparatus as claimed in claim 12 , further comprising a pixel-defining layer exposing a center portion of the pixel electrode and covering an edge of the pixel electrode, the pixel defining layer define pixels.
17. The display apparatus as claimed in claim 12 , wherein the intermediate layer includes an emission layer.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
September 4, 2018
November 26, 2019
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