The present disclosure provides an integrated circuit (IC) method in accordance with some embodiments. The method includes building a mask model to simulate a mask image and a compound lithography computational model to simulate a wafer pattern; calibrating the mask model using a measured mask image; calibrating the compound lithography computational model using a measured wafer data and the calibrated mask model; and performing an optical proximity correction (OPC) process to an IC pattern using the calibrated compound computational model, thereby generating a mask pattern for mask fabrication.
Legal claims defining the scope of protection. Each claim is shown in both the original legal language and a plain English translation.
1. An integrated circuit (IC) method comprising: building a mask model to simulate an aerial mask image of a mask optically projected on a wafer through projection optics using an optical radiation energy of a lithography process, and a compound lithography computational (CLC) model to simulate a wafer pattern; calibrating the mask model using a measured aerial mask image of the mask optically projected on a second wafer through the projection optics; calibrating the compound lithography computational model using a measured wafer data and the calibrated mask model; and performing an optical proximity correction (OPC) process to an IC pattern using the calibrated compound computational model, thereby generating a mask pattern for mask fabrication.
This technical summary describes a method for improving lithography processes in integrated circuit (IC) manufacturing. The method addresses the challenge of accurately simulating and correcting optical proximity effects during lithography, which can distort IC patterns on wafers. The approach involves building two key models: a mask model and a compound lithography computational (CLC) model. The mask model simulates the aerial mask image projected onto a wafer through projection optics, while the CLC model simulates the resulting wafer pattern. The mask model is calibrated using measured aerial mask images obtained by optically projecting the mask onto a second wafer. The CLC model is then calibrated using measured wafer data and the calibrated mask model. Finally, an optical proximity correction (OPC) process is applied to the IC pattern using the calibrated CLC model, generating a corrected mask pattern for fabrication. This method enhances lithography accuracy by refining the simulation models with real-world measurements, ensuring better pattern fidelity on the wafer.
2. The IC method of claim 1 , further comprising: making a mask based on the mask pattern; and performing the lithography process to the wafer using the mask, wherein: the making a mask includes coating a first resist layer to the mask, performing an electron-beam writing process according to the mask pattern to pattern the first resist layer, and etching the mask through the patterned first resist layer; and the performing a lithography process to the wafer includes coating a second resist layer to the wafer, and exposing the second resist layer using the mask to form a pattern second resist layer on the wafer.
This invention relates to integrated circuit (IC) manufacturing, specifically a method for fabricating a mask and performing a lithography process on a wafer. The problem addressed is the need for precise pattern transfer from a mask pattern to a wafer during semiconductor fabrication. The method involves creating a mask by coating a first resist layer onto the mask substrate, then using an electron-beam writing process to pattern the resist layer according to the mask pattern. The patterned resist layer is then used as an etch mask to transfer the pattern into the underlying mask material. The mask is subsequently used in a lithography process on a wafer, where a second resist layer is coated onto the wafer and exposed through the mask to form a patterned resist layer on the wafer. This patterned resist layer can then be used for further semiconductor processing steps, such as etching or doping. The method ensures accurate pattern replication from the mask to the wafer, which is critical for high-precision IC manufacturing. The use of electron-beam writing allows for high-resolution patterning, while the lithography process enables efficient pattern transfer to the wafer. This approach is particularly useful in advanced semiconductor fabrication where feature sizes are extremely small and precision is paramount.
3. The IC method of claim 1 , wherein the measured aerial mask image is measured with an instrument selected from a lithography exposure system and an image measurement system (IMS) using an optical radiation source selected from ultra-violet (UV), deep UV, extreme UV (EUV) sources; and the IC method further comprising measuring a wafer pattern before the calibrating the compound lithography computational model.
This invention relates to integrated circuit (IC) manufacturing, specifically improving lithography processes by calibrating a compound lithography computational model. The problem addressed is the need for accurate pattern transfer in semiconductor fabrication, where variations in lithography systems and wafer processing can lead to deviations from intended designs. The solution involves measuring an aerial mask image using either a lithography exposure system or an image measurement system (IMS) with an optical radiation source such as UV, deep UV, or EUV. Additionally, the method includes measuring a wafer pattern before calibrating the computational model. This ensures that the model accounts for both the mask's aerial image and the actual wafer pattern, improving accuracy in predicting lithography outcomes. The calibrated model can then be used to optimize exposure settings, correct distortions, or enhance pattern fidelity in subsequent IC manufacturing steps. The approach leverages advanced optical measurement techniques to refine computational models, addressing challenges in high-precision semiconductor fabrication.
4. The IC method of claim 1 , further comprising: receiving an IC design layout including the IC pattern; and forming a wafer target based on the IC pattern before the performing an OPC process to the IC pattern.
This invention relates to integrated circuit (IC) manufacturing, specifically improving optical proximity correction (OPC) processes to enhance pattern fidelity on wafers. The problem addressed is the need to optimize IC pattern transfer from design to wafer by accounting for lithographic distortions early in the process. The method involves receiving an IC design layout containing the IC pattern and forming a wafer target based on this pattern before performing OPC. The wafer target represents the desired final pattern on the wafer after lithography and etching. By establishing this target before OPC, the correction process can be more accurately tailored to minimize deviations between the intended design and the actual wafer pattern. This approach improves pattern fidelity by ensuring OPC adjustments are made with a clear understanding of the final lithographic constraints. The method also includes performing OPC on the IC pattern to compensate for lithographic distortions, such as diffraction and proximity effects, which can distort the pattern during exposure. The OPC process modifies the design layout to counteract these distortions, ensuring the printed pattern on the wafer closely matches the intended design. The wafer target serves as a reference to guide these corrections, improving accuracy. This technique is particularly useful in advanced semiconductor manufacturing where precise pattern transfer is critical for device performance and yield. By integrating wafer target formation early in the OPC workflow, the method enhances the overall lithographic process, reducing errors and improving manufacturing efficiency.
5. The method of claim 4 , wherein the performing an OPC process includes modifying the IC pattern; simulating the IC pattern using the compound lithography computational model to generate a wafer contour of the IC pattern; determining a difference between the wafer contour and the wafer target; and repeating the modifying of the IC pattern and the simulating of the IC pattern if the difference is beyond a tolerable range.
The field of integrated circuit (IC) manufacturing involves optical proximity correction (OPC) to compensate for distortions that occur during lithography. A key challenge is ensuring that the final wafer pattern matches the intended design within acceptable tolerances. Traditional OPC methods often rely on iterative adjustments to the IC pattern, but these may not account for complex interactions in advanced lithography processes, such as compound lithography, where multiple exposures are used. This invention addresses this problem by improving the OPC process for IC manufacturing. The method involves modifying the IC pattern to compensate for distortions, then simulating the modified pattern using a compound lithography computational model to predict the resulting wafer contour. The predicted wafer contour is compared to the desired wafer target, and if the difference exceeds a tolerable range, the IC pattern is further modified and the simulation is repeated. This iterative process continues until the difference falls within acceptable limits, ensuring high-fidelity pattern transfer to the wafer. The approach enhances accuracy in advanced lithography techniques, particularly those involving multiple exposure steps, by dynamically refining the IC pattern based on computational predictions.
6. The IC method of claim 5 , wherein the mask model is defined by a first formula to generate the aerial mask image according to the IC pattern; and the compound lithography computational model is defined by a second formula to generate a wafer contour according to the mask model and a resist model.
This invention relates to integrated circuit (IC) lithography simulation, specifically improving the accuracy of predicting wafer contours during the semiconductor manufacturing process. The problem addressed is the need for precise computational models to simulate how IC patterns on a mask translate into actual wafer features, accounting for variations in resist behavior and lithographic processes. The invention describes a method for generating a wafer contour using a multi-step computational approach. First, a mask model is defined by a mathematical formula that converts an IC pattern into an aerial mask image, representing the light distribution projected onto a wafer. This mask model captures the optical effects of the lithography system. Second, a compound lithography computational model is defined by another mathematical formula that uses the mask model along with a resist model to generate the final wafer contour. The resist model accounts for how the photoresist material reacts to the light exposure, including chemical and physical interactions that affect feature formation. By combining these models, the method provides a more accurate prediction of the actual wafer features produced during lithography, enabling better process optimization and defect reduction in semiconductor manufacturing. The approach is particularly useful for advanced nodes where feature sizes are extremely small, and traditional simulation methods may lack precision.
7. The IC method of claim 1 , wherein the building of the CLC model includes simulating a wafer etching process.
This invention relates to integrated circuit (IC) manufacturing, specifically improving the accuracy of compact layout-aware (CLC) models used in semiconductor design. The problem addressed is the lack of precision in traditional CLC models when simulating real-world fabrication processes, particularly wafer etching, which can lead to inaccuracies in predicting device performance and yield. The invention describes a method for enhancing CLC models by incorporating detailed simulations of wafer etching processes. This involves modeling the physical and chemical interactions that occur during etching, including material removal rates, mask erosion, and feature distortion. By integrating these simulations into the CLC model, the method provides a more accurate representation of how actual fabrication processes affect IC performance. The enhanced model can then be used to optimize layout designs before manufacturing, reducing the need for costly iterations and improving overall yield. The method ensures that the CLC model accounts for variations in etching behavior across different regions of the wafer, including edge effects and non-uniformities. This allows designers to predict how etching will impact critical dimensions, sidewall profiles, and other geometric features, leading to more reliable IC designs. The approach is particularly useful for advanced nodes where precision in fabrication is critical.
8. The IC method of claim 1 , wherein the measured wafer data includes data of a wafer etching process that transfers a material layer pattern into the wafer pattern.
The invention relates to integrated circuit (IC) manufacturing, specifically addressing challenges in monitoring and controlling wafer etching processes. During IC fabrication, precise etching is critical to transfer material layer patterns into the wafer with high accuracy. However, variations in etching processes can lead to defects or deviations from intended patterns, impacting device performance and yield. The invention provides a method for analyzing wafer data to improve etching process control. The method involves measuring wafer data during or after the etching process, where the data includes information about the transfer of a material layer pattern into the wafer. This data may include measurements of etch depth, uniformity, sidewall profile, or other critical parameters that affect pattern fidelity. By collecting and analyzing this data, the method enables real-time or post-process adjustments to optimize etching conditions, such as etch time, gas flow, or plasma parameters, to ensure consistent and accurate pattern transfer. The method may also integrate with other process monitoring techniques, such as metrology or inspection systems, to provide comprehensive feedback for process optimization. The goal is to reduce defects, improve yield, and enhance the overall reliability of IC manufacturing by ensuring precise pattern transfer during etching. This approach is particularly useful in advanced semiconductor nodes where tight tolerances and high precision are required.
9. The IC method of claim 1 , wherein the aerial mask image is an image of the mask optically projected on a wafer through a lithography exposure system.
This invention relates to integrated circuit (IC) manufacturing, specifically improving lithography processes by analyzing aerial mask images. The problem addressed is ensuring accurate pattern transfer from a photomask to a wafer during lithography, where distortions or imperfections in the optical projection system can degrade pattern fidelity. The solution involves capturing an aerial mask image, which is an optical projection of the mask pattern onto a wafer through a lithography exposure system. This image represents how the mask pattern appears when illuminated and projected, accounting for system-specific optical effects like diffraction, aberrations, and focus variations. By analyzing this aerial image, manufacturers can detect and correct deviations from the intended design, improving yield and performance. The method may include comparing the aerial image to a reference or simulating its impact on final wafer patterns. This approach enhances process control by directly assessing the optical projection quality rather than relying solely on mask design data or post-exposure wafer measurements. The technique is applicable to advanced lithography nodes where precision is critical, such as EUV or deep UV processes.
10. An integrated circuit (IC) method comprising: measuring a mask image of a mask optically projected on a wafer with an instrument selected from a lithography exposure system and an image measurement system (IMS) using an optical radiation source selected from ultra-violet (UV), deep UV, extreme UV (EUV) sources; calibrating a mask model using the measured mask image; calibrating a compound lithography computational (CLC) model using a measured wafer data and the calibrated mask model; and performing an optical proximity correction (OPC) process to an IC pattern using the calibrated CLC model, thereby generating a mask pattern for mask fabrication.
This invention relates to integrated circuit (IC) manufacturing, specifically improving lithography processes by enhancing mask pattern correction techniques. The problem addressed is the need for accurate mask pattern generation to ensure precise optical projection onto wafers, which is critical for high-resolution IC fabrication. Traditional methods often suffer from inaccuracies due to variations in mask imaging and wafer exposure, leading to defects or performance issues in the final IC. The method involves measuring a mask image projected onto a wafer using either a lithography exposure system or an image measurement system (IMS), with optical radiation sources such as UV, deep UV, or EUV. The measured mask image is then used to calibrate a mask model, which accounts for distortions or imperfections in the mask. Next, a compound lithography computational (CLC) model is calibrated using wafer data and the calibrated mask model, integrating both mask and wafer-level variations. Finally, an optical proximity correction (OPC) process is applied to the IC pattern using the calibrated CLC model, generating an optimized mask pattern for fabrication. This approach improves lithography accuracy by accounting for both mask and wafer-level variations, reducing defects and enhancing IC performance. The method is applicable to advanced lithography techniques, including EUV, where precision is critical.
11. The IC method of claim 10 , further comprising: receiving an IC design layout including the IC pattern; and forming a wafer target based on the IC pattern before the performing an OPC process to the IC pattern.
This invention relates to integrated circuit (IC) manufacturing, specifically improving optical proximity correction (OPC) processes to enhance pattern fidelity on semiconductor wafers. The problem addressed is the need for more accurate and efficient OPC adjustments to compensate for optical distortions during lithography, ensuring precise pattern transfer from design to wafer. The method involves receiving an IC design layout containing the IC pattern and forming a wafer target based on this pattern before performing OPC. The wafer target represents the desired physical structure on the wafer, accounting for lithography limitations. By generating this target before OPC, the process can more effectively adjust the pattern to minimize distortions caused by optical effects like diffraction and interference. This pre-OPC target formation ensures that the final OPC adjustments are optimized for the specific lithography conditions, improving yield and reducing defects. The method may also include analyzing the IC pattern to identify critical features requiring correction, simulating the lithography process to predict distortions, and iteratively refining the pattern until the wafer target matches the design intent. The approach is particularly useful for advanced nodes where feature sizes are near the resolution limits of lithography tools. By integrating wafer target formation early in the OPC workflow, the invention enhances pattern accuracy and manufacturability.
12. The method of claim 11 , wherein the performing an OPC process includes modifying the IC pattern; simulating the IC pattern using the CLC model to generating a wafer contour of the IC pattern; determining a difference between the wafer contour and the wafer target; and repeating above steps if the difference is beyond a tolerable range.
This invention relates to optical proximity correction (OPC) in integrated circuit (IC) manufacturing, specifically improving pattern fidelity by refining IC designs before lithography. The problem addressed is ensuring that the final wafer pattern matches the intended design within acceptable tolerances, as optical distortions during lithography can degrade pattern accuracy. The method involves modifying an IC pattern and simulating its behavior using a critical dimension (CD) calibration (CLC) model to predict the resulting wafer contour. The predicted wafer contour is compared to the desired wafer target, and if the difference exceeds a tolerable range, the process is repeated iteratively. This iterative refinement continues until the wafer contour aligns with the target within acceptable limits, ensuring high-precision pattern transfer during lithography. The CLC model accounts for variations in lithography conditions, such as exposure dose and focus, to accurately predict how the IC pattern will be printed on the wafer. By adjusting the IC pattern based on these simulations, the method compensates for optical distortions, improving manufacturing yield and device performance. This approach is particularly useful in advanced semiconductor nodes where feature sizes are extremely small, and precision is critical.
13. The IC method of claim 12 , wherein the mask model is defined in a formula I(x, mp), wherein mp is a set of mask model parameters including parameters determined by historic manufacturing data, and I(x, mp) is a mask image function that simulates an image of a pattern of a mask onto a semiconductor wafer during a lithography exposing process; and the CLC model is defined in a formula W(x)=Φ 2 (Φ 1 (I(x, mp))), wherein x represents a location in a 2-D Cartesian coordinate; W(x) defines a simulated wafer contour that simulates a pattern transferred to the semiconductor wafer by the lithography exposing process and an etching process; Φ 1 defines a resist pattern function that simulates characteristics of a photoresist coated on the semiconductor wafer, the characteristics of the photoresist including characteristics of a resist reaction with photons and a resist development; and Φ 2 defines a wafer pattern function that simulates characteristics of an etching process applied to the semiconductor wafer, the characteristics of the etching process including the characteristics of transferring a contour of a pattern to a material layer of the semiconductor wafer.
This invention relates to semiconductor manufacturing, specifically to integrated circuit (IC) modeling for lithography and etching processes. The technology addresses the challenge of accurately predicting the final wafer pattern after lithography exposure and subsequent etching, which is critical for optimizing mask designs and improving yield. The method involves defining a mask model and a combined lithography and etching (CLC) model. The mask model is represented by a function I(x, mp), where mp is a set of mask parameters derived from historical manufacturing data. This function simulates how a mask pattern is projected onto a semiconductor wafer during lithography exposure. The CLC model is defined by W(x) = Φ2(Φ1(I(x, mp))), where x is a 2D coordinate location. The function W(x) simulates the final wafer contour after both lithography and etching. Φ1 represents a resist pattern function that models photoresist behavior, including its reaction to photons and development. Φ2 represents a wafer pattern function that models the etching process, including how the resist pattern is transferred to the underlying material layer. By combining these models, the invention enables accurate simulation of the entire pattern transfer process, allowing for better mask optimization and process control in semiconductor manufacturing.
14. The IC method of claim 10 , further comprising making a mask based on the mask pattern subsequent to the calibrating a mask model.
This invention relates to integrated circuit (IC) manufacturing, specifically to improving mask pattern calibration to enhance lithography accuracy. The problem addressed is the need for precise mask pattern adjustments to compensate for distortions during the photolithography process, ensuring accurate feature replication on the wafer. The method involves generating an initial mask pattern for IC fabrication. A mask model is calibrated by comparing simulated lithography results of the initial pattern with target design specifications. This calibration refines the mask model to account for process variations and optical proximity effects. After calibration, a final mask is produced based on the adjusted mask pattern. The mask is then used in a lithography system to transfer the pattern onto a wafer, achieving higher fidelity to the original design. The invention further includes additional steps such as simulating the lithography process using the calibrated mask model to predict pattern distortions and iteratively refining the mask pattern until the simulated results meet predefined accuracy thresholds. This ensures that the final mask compensates for known process variations, reducing defects and improving yield in IC manufacturing. The method is particularly useful in advanced semiconductor nodes where feature sizes are extremely small, and precision is critical.
15. The IC method of claim 14 , further comprising performing a lithography process to a wafer using the mask.
The invention relates to integrated circuit (IC) manufacturing, specifically improving lithography processes for wafer patterning. The problem addressed is the need for precise and efficient mask-based lithography to enhance IC fabrication accuracy and yield. The method involves using a mask to pattern a wafer during lithography, where the mask is designed to optimize exposure and alignment. The mask may include features such as alignment marks, critical dimension (CD) control structures, or phase-shifting elements to improve resolution and reduce defects. The lithography process is performed using the mask to transfer the desired pattern onto the wafer, ensuring high precision in feature placement and dimensions. The method may also include pre- and post-lithography steps, such as mask inspection, wafer cleaning, or resist development, to ensure optimal results. The invention aims to enhance lithography accuracy, reduce defects, and improve overall IC manufacturing efficiency by leveraging advanced mask designs and process controls.
16. The IC method of claim 15 , further comprising constructing the mask model to simulate the mask image and a CLC model to simulate a wafer contour, wherein the CLC model includes effects of an etching process; measuring a mask image before the calibrating a mask model; and measuring a wafer pattern before the calibrating of the CLC model, wherein the measured wafer data includes data on a wafer etching process.
This invention relates to integrated circuit (IC) manufacturing, specifically improving lithography and etching process accuracy. The method involves creating a mask model to simulate the mask image and a critical layer contour (CLC) model to simulate the final wafer pattern, accounting for etching process effects. The mask model is calibrated using measured mask image data, while the CLC model is calibrated using measured wafer pattern data, which includes information on the etching process. By incorporating these measurements, the models more accurately predict the final wafer pattern, reducing errors in IC fabrication. The approach ensures that variations in the mask and etching process are accounted for, improving yield and performance in semiconductor manufacturing. The method integrates mask and wafer measurements to refine the models, enabling better control over the lithography and etching steps. This reduces defects and enhances the precision of the final IC structures.
17. The method of claim 14 , further comprising performing a fracturing process to the mask pattern, thereby generating an electron-beam shot map to be used in an electron-beam lithography process to pattern the mask.
This invention relates to the field of semiconductor manufacturing, specifically to the creation of mask patterns for electron-beam lithography. The problem addressed is the efficient generation of electron-beam shot maps from mask patterns, which is a critical step in high-precision lithography processes. The method involves performing a fracturing process on a mask pattern to convert it into a shot map, which is a set of instructions for an electron-beam lithography system. The fracturing process breaks down the mask pattern into smaller, manageable shapes that the electron beam can accurately expose. This step ensures that the final mask pattern is faithfully reproduced during lithography, which is essential for producing high-resolution semiconductor devices. The fracturing process optimizes the shot map to minimize exposure time and improve accuracy, addressing challenges in modern semiconductor manufacturing where feature sizes continue to shrink. The resulting shot map is then used in an electron-beam lithography system to pattern the mask, enabling the production of advanced integrated circuits with nanometer-scale features. This method enhances the efficiency and precision of mask patterning, which is crucial for maintaining yield and performance in semiconductor fabrication.
18. The method of claim 17 , further comprising performing a mask making process to the mask using the electron-beam shot map, wherein the mask making process includes the electron-beam lithography process.
This invention relates to mask fabrication for semiconductor manufacturing, specifically addressing the challenge of efficiently producing high-precision masks using electron-beam lithography. The method involves generating an electron-beam shot map, which defines the exposure patterns for a mask substrate. This shot map is used to guide an electron-beam lithography process, where a focused electron beam selectively exposes a resist layer on the mask substrate according to the shot map. The exposed resist is then developed to form a patterned resist layer, which serves as a template for subsequent etching or other material removal processes to create the final mask structure. The electron-beam lithography process ensures high-resolution patterning, essential for advanced semiconductor devices. The method may also include additional steps such as resist coating, post-exposure baking, and inspection to ensure mask quality. By optimizing the electron-beam shot map and lithography parameters, the invention enables precise and efficient mask fabrication, reducing defects and improving yield in semiconductor manufacturing.
19. An integrated circuit (IC) design system, comprising a mask data module designed to collect mask imaging data, wherein the mask data module includes: a radiation source to generate a light radiation selected from ultra-violet (UV), deep UV, and extreme UV (EUV) light; projection optics to project a mask image of a mask to an image stage, wherein the mask image is designed to mimic an image of the mask projected onto a wafer in a lithography system in a lithography exposing process; and an image detector to collect the mask imaging data at the image stage, the mask imaging data includes the mask image; a wafer data module designed to collect wafer manufacturing data from a wafer making process, wherein the wafer manufacturing data includes wafer etching data; a first calibration module designed to calibrate a mask model based on the mask imaging data; a second calibration module designed to calibrate a compound lithography computational model based on the wafer manufacturing data; and an optical proximity correction (OPC) module designed to perform an OPC process using the mask model and the compound lithography computational mode.
This invention relates to an integrated circuit (IC) design system that improves lithography accuracy by calibrating mask and wafer manufacturing data to enhance optical proximity correction (OPC). The system addresses challenges in semiconductor manufacturing where variations in mask imaging and wafer etching processes lead to inaccuracies in IC fabrication. The system includes a mask data module that collects mask imaging data using a radiation source emitting UV, deep UV, or EUV light. Projection optics project a mask image onto an image stage, simulating the lithography process, while an image detector captures the mask imaging data. A wafer data module gathers wafer manufacturing data, particularly wafer etching data, from the wafer-making process. Two calibration modules refine the system’s models: the first calibrates a mask model using the mask imaging data, while the second calibrates a compound lithography computational model using the wafer manufacturing data. An OPC module then applies these calibrated models to perform OPC, adjusting the mask design to compensate for lithography distortions and improve pattern fidelity on the wafer. By integrating mask and wafer data, the system enhances OPC accuracy, reducing defects and improving yield in semiconductor manufacturing. The use of high-precision imaging and real manufacturing data ensures better alignment between design and fabrication.
20. The IC design system of claim 19 , further comprising a model builder designed to build the mask model and the compound lithography computational model.
The invention relates to integrated circuit (IC) design systems, specifically addressing challenges in mask optimization and lithography simulation for advanced semiconductor manufacturing. The system improves the accuracy and efficiency of lithography processes by generating optimized mask patterns and simulating their performance under compound lithography techniques. A key component is a model builder that constructs both a mask model and a compound lithography computational model. The mask model represents the physical mask design, while the compound lithography computational model simulates the interaction of multiple lithography exposures to predict final wafer patterns. This dual-model approach enhances the system's ability to account for complex lithographic effects, such as interference and distortion, which are critical in modern nanometer-scale fabrication. The system integrates these models to refine mask designs iteratively, ensuring higher yield and performance in semiconductor manufacturing. By automating the generation and refinement of these models, the system reduces manual effort and improves the precision of lithography simulations, addressing the growing complexity of IC design and fabrication processes.
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November 15, 2017
December 3, 2019
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