Patentable/Patents/US-10510690
US-10510690

Wafer level package (WLP) and method for forming the same

PublishedDecember 17, 2019
Assigneenot available in USPTO data we have
Inventorsnot available in USPTO data we have
Technical Abstract

A semiconductor device structure and method for forming the same are provided. The semiconductor device structure includes a substrate and a conductive pad formed on the substrate. The semiconductor device structure includes a protection layer formed over the conductive pad and a post-passivation interconnect (PPI) structure formed at least in the protection layer. The PPI structure is electrically connected to the conductive pad. The semiconductor device structure also includes a first moisture-resistant layer formed over the protection layer, and the protection layer and the first moisture-resistant layer are made of different materials. The semiconductor device structure further includes an under bump metallurgy (UBM) layer formed over the first moisture-resistant layer and connected to the PPI structure.

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Patent Metadata

Filing Date

August 14, 2018

Publication Date

December 17, 2019

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