Low distortion successive approximation register (SAR) analog-to-digital converters (ADCs) and associated methods

An ADC device comprises a comparator having an output, a first input, and a second input. And the ADC includes a SAR configured to receive the output of the comparator as an input and to generate based thereon a parallel digital output having a most significant bit (MSB) and a plurality of less significant bits associated with a reference voltage. The ADC also includes a DAC configured to receive the parallel digital output from the SAR and to generate based thereon an internal analog signal, the internal analog signal applied as the first input to the comparator. The DAC further includes a capacitor network coupled to the first input having a redistribution capacitor coupled to a first voltage that is greater than the reference voltage such that a ratio N is equal to the reference voltage divided by the first voltage. The DAC also includes one or more first capacitors also coupled to the first voltage, where at least one first capacitor is associated with the MSB. The DAC further including and a plurality of second capacitors coupled to the reference voltage, wherein the redistribution capacitor having a capacitive value that is equal to (1−N) times the total capacitance of a parallel combination of the one or more first capacitors. And the second capacitors are associated with less significant bits, and an input voltage line carrying an input voltage (VIN) switchably coupled to the first input or switchably coupled to the second input.