Methods and systems for quantifying and correcting for non-uniformities in images used for metrology operations are disclosed. A metrology area image of a wafer and a design clip may be used. The metrology area image may be a scanning electron microscope image. The design clip may be the design clip of the wafer or a synthesized design clip. Tool distortions, including electron beam distortions, can be quantified and corrected. The design clip can be applied to the metrology area image to obtain a synthesized image such that one or more process change variations are suppressed and one or more tool distortions are enhanced.
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1. A method of compensating for scanning electron microscope beam distortion-induced metrology error comprising: receiving, at a processor, a metrology area image of a wafer, wherein the metrology area image is a microscopy image of the wafer; receiving, at the processor, a design clip from a storage medium, wherein the design clip includes one or more design polygons and corresponds to an area of the wafer in the metrology area image; applying the design clip to the metrology area image using the processor with an image comparison and rendering process thereby obtaining a synthesized image, wherein one or more process change variations are suppressed and one or more tool distortions are enhanced; and performing metrology operations on the synthesized image.
This technical summary describes a method for correcting metrology errors in scanning electron microscope (SEM) imaging caused by beam distortion. The method addresses the challenge of accurately measuring semiconductor wafer features when SEM beam distortions introduce errors, affecting precision in critical dimension (CD) measurements and defect detection. The process begins by acquiring a metrology area image of a wafer using SEM, capturing high-resolution microscopic details. A design clip, containing design polygons representing the intended wafer pattern, is retrieved from storage. The design clip corresponds to the same wafer area as the SEM image. The method then applies the design clip to the SEM image using an image comparison and rendering process. This step suppresses process variations (e.g., lithography or etch inconsistencies) while enhancing tool-induced distortions (e.g., beam aberrations or charging effects). The resulting synthesized image isolates distortion artifacts, allowing for accurate metrology operations. These operations may include measuring feature dimensions, detecting defects, or analyzing pattern fidelity. By separating tool distortions from actual process variations, the method improves the reliability of SEM-based metrology in semiconductor manufacturing.
2. The method of claim 1 , wherein the design clip is a design for the wafer.
A method for semiconductor manufacturing involves creating a design clip for a wafer, where the design clip is specifically tailored to the wafer's design. The method includes generating a design clip that represents a portion of the wafer's layout, which can be used for testing, verification, or optimization of the semiconductor manufacturing process. The design clip is derived from the wafer's overall design, ensuring that it accurately reflects the structural and functional characteristics of the target wafer. This approach allows for precise analysis of specific regions within the wafer, improving yield and performance. The method may also involve simulating the design clip under various conditions to predict potential
3. The method of claim 1 , wherein the design clip is a synthesized design clip, and wherein the synthesized design clip is generated by a method comprising: generating the synthesized design clip using the process change variations with a machine algorithm; and communicating the synthesized design clip to the storage medium.
This invention relates to semiconductor manufacturing, specifically addressing the challenge of managing process variations in integrated circuit (IC) design. Process variations during fabrication can lead to performance inconsistencies, requiring designers to account for these variations during the design phase. The invention provides a method to generate and utilize synthesized design clips that incorporate process change variations, enabling more accurate and robust IC design verification. The method involves creating a synthesized design clip by applying process change variations to a base design using a machine algorithm. This algorithm simulates how manufacturing variations might affect the design, generating a modified version that reflects potential real-world deviations. The synthesized design clip is then stored in a storage medium, making it available for further analysis or verification. This approach allows designers to test and optimize their designs under various process conditions, improving yield and reliability. The machine algorithm used in this process can be trained or configured to model specific types of process variations, such as variations in transistor dimensions, doping levels, or other fabrication parameters. By generating multiple synthesized design clips, designers can assess the impact of different process scenarios on the final IC performance. This method enhances the design verification process by providing a more comprehensive understanding of how process variations influence circuit behavior.
4. The method of claim 3 , wherein the synthesized design clip is generated by a method further comprising: receiving images and data from one or more process modulated wafers at a machine learning module; and learning the process change variations at the machine learning module using the machine algorithm.
This invention relates to semiconductor manufacturing, specifically improving yield by analyzing process variations using machine learning. The method involves generating a synthesized design clip, which is a representative sample of a semiconductor design, to model and predict process variations during wafer fabrication. The synthesized clip is created by receiving images and data from wafers that have undergone process modulation, where intentional variations are introduced to simulate different manufacturing conditions. A machine learning module processes this data to learn and identify patterns in how these variations affect the final product. The learned variations are then used to optimize the design or manufacturing process, reducing defects and improving yield. The machine learning algorithm adapts to new data, continuously refining its predictions to account for evolving process conditions. This approach enables proactive adjustments in semiconductor fabrication, ensuring higher consistency and reliability in production.
5. The method of claim 3 , wherein the machine algorithm is a deep learning algorithm.
A system and method for improving machine learning model performance by dynamically adjusting training parameters based on real-time feedback. The technology addresses the challenge of optimizing machine learning models in environments where data distributions shift over time, leading to degraded performance. Traditional static training approaches fail to adapt to these changes, resulting in suboptimal accuracy and efficiency. The method involves a feedback loop where a machine learning model processes input data and generates outputs. Performance metrics, such as accuracy or error rates, are continuously monitored. Based on these metrics, training parameters—such as learning rates, batch sizes, or model architectures—are dynamically adjusted to improve performance. The system may also incorporate user feedback or external data sources to refine adjustments. In one implementation, the machine algorithm is a deep learning algorithm, which leverages neural networks to process complex data patterns. The dynamic adjustment mechanism ensures that the deep learning model remains effective even as input data characteristics evolve. This approach enhances model robustness and adaptability in real-world applications, such as autonomous systems, predictive analytics, or adaptive control systems. The system may also include validation steps to ensure that adjustments do not compromise model stability or generalization.
6. The method of claim 1 , wherein the metrology area image is a scanning electron microscope image.
The invention relates to metrology techniques for semiconductor manufacturing, specifically improving the accuracy of measurements in semiconductor devices. The problem addressed is the need for precise and reliable metrology data to ensure consistent device performance, particularly in advanced semiconductor fabrication where feature sizes are extremely small. Traditional optical metrology techniques often lack the resolution required for these tiny structures, leading to measurement inaccuracies. The invention involves a method for obtaining high-resolution metrology data by using a scanning electron microscope (SEM) to capture images of a metrology area on a semiconductor wafer. The SEM image provides detailed structural information at the nanoscale, enabling precise measurements of critical dimensions and other features. The method may include preprocessing the SEM image to enhance contrast, reduce noise, or correct distortions, ensuring accurate feature extraction. Additionally, the method may involve comparing the SEM image with a reference pattern or model to detect deviations, such as defects or dimensional variations, which can impact device performance. The SEM-based approach allows for higher resolution than optical techniques, improving measurement accuracy and reliability in semiconductor manufacturing processes. This method is particularly useful in advanced node fabrication, where traditional optical metrology falls short.
7. The method of claim 1 , wherein the metrology area image is an average of a plurality of scanning electron microscope images.
A method for improving the accuracy of metrology measurements in semiconductor manufacturing involves capturing multiple scanning electron microscope (SEM) images of a metrology area and averaging them to generate a final metrology area image. The averaging process reduces noise and enhances the signal-to-noise ratio, leading to more precise measurements of critical dimensions or other features. This technique is particularly useful in semiconductor inspection and process control, where high-resolution imaging is essential for detecting defects or verifying manufacturing tolerances. By combining multiple SEM images, the method mitigates the effects of random noise, electron beam fluctuations, or sample charging, which can distort individual images. The averaged image provides a more stable and reliable representation of the metrology area, improving the accuracy of subsequent measurements. This approach is applicable to various semiconductor structures, including transistors, interconnects, or other nanoscale features, where precise dimensional control is critical. The method may be integrated into automated inspection systems or used in conjunction with other metrology techniques to enhance overall process monitoring and quality control.
8. The method of claim 1 , wherein the storage medium is a persistent, non-transient storage medium.
A system and method for data storage and retrieval involves a storage medium that is persistent and non-transient, ensuring data remains intact even after power loss or system shutdown. The storage medium is designed to retain information without requiring continuous power, distinguishing it from volatile memory solutions. This method is particularly useful in applications where data integrity and reliability are critical, such as in enterprise storage systems, databases, or embedded systems where power interruptions are common. The persistent storage medium may include technologies like solid-state drives (SSDs), hard disk drives (HDDs), or other non-volatile memory devices. The system may further include mechanisms for error detection, correction, and data redundancy to enhance reliability. By using a persistent storage medium, the method ensures that stored data remains accessible and uncorrupted over time, addressing the problem of data loss due to power failures or system crashes. The method may also incorporate encryption or other security measures to protect stored data from unauthorized access. Overall, the invention provides a robust solution for maintaining data integrity in environments where power stability cannot be guaranteed.
9. The method of claim 1 , further comprising obtaining the metrology area image of the wafer using a scanning electron microscope.
A method for semiconductor wafer inspection involves capturing a metrology area image of a wafer using a scanning electron microscope (SEM). The SEM provides high-resolution imaging to detect defects or measure critical dimensions on the wafer surface. This imaging technique is particularly useful for identifying sub-micron features and defects that may impact device performance. The SEM generates an electron beam that scans the wafer surface, and the resulting secondary or backscattered electrons form an image, which is then analyzed to assess wafer quality. The method may also include additional steps such as preprocessing the image to enhance contrast or noise reduction, followed by defect detection algorithms to identify anomalies. The SEM-based imaging ensures high precision, making it suitable for advanced semiconductor manufacturing processes where accuracy is critical. This approach helps manufacturers maintain yield and reliability by detecting defects early in the production cycle. The method is applicable to various semiconductor fabrication stages, including post-etch, post-deposition, and post-CMP (chemical-mechanical planarization) processes. The use of SEM imaging provides detailed surface information, enabling precise defect classification and measurement. This technique is part of a broader inspection system that may integrate multiple imaging modalities to improve defect detection accuracy.
10. The method of claim 1 , further comprising tuning system components of a wafer metrology tool to reduce distortion based on the metrology operations.
A wafer metrology tool is used to measure and analyze semiconductor wafers during manufacturing, ensuring precision in critical dimensions and defect detection. However, metrology operations can introduce distortions, such as measurement inaccuracies or tool-induced artifacts, which degrade the reliability of the results. These distortions arise from factors like environmental fluctuations, mechanical vibrations, or miscalibrated components, leading to inconsistent or erroneous data that can compromise yield and process control. To address this, a method involves tuning system components of the wafer metrology tool to reduce distortion during metrology operations. The tuning process adjusts parameters of the tool's hardware or software to minimize measurement errors. For example, optical components may be recalibrated to correct for light path deviations, while mechanical stages may be realigned to reduce vibrations. Additionally, environmental controls, such as temperature or humidity regulation, can be optimized to stabilize operating conditions. The tuning may be performed dynamically during operation or as part of a periodic calibration routine. By actively mitigating distortions, the method enhances the accuracy and repeatability of wafer measurements, improving overall manufacturing quality and efficiency. This approach ensures that the metrology tool delivers consistent, high-fidelity data for process monitoring and defect analysis.
11. A system for compensating for distortion-induced metrology error comprising: a wafer metrology tool configured to produce a metrology area image, wherein the metrology area image is a microscopy image of the wafer; and a processor in electronic communication with the wafer metrology tool, wherein the processor is configured to receive and apply a design clip to the metrology area image using an image comparison and rendering process such that one or more process change variations are suppressed and one or more tool distortions are enhanced thereby obtaining a synthesized image, wherein the design clip includes one or more design polygons and corresponds to an area of the wafer in the metrology area image.
This system addresses distortion-induced metrology errors in semiconductor wafer inspection. During wafer metrology, optical distortions from the imaging tool can introduce inaccuracies, making it difficult to distinguish between actual process variations and tool-induced artifacts. The system compensates for these errors by enhancing tool distortions while suppressing process variations, improving measurement accuracy. The system includes a wafer metrology tool that captures a microscopy image of the wafer. A processor receives this image and applies a design clip—a set of design polygons corresponding to the imaged wafer area—using an image comparison and rendering process. This process compares the metrology image with the design clip to isolate and enhance tool distortions while minimizing the visibility of process variations. The result is a synthesized image where tool distortions are more prominent, allowing for better error correction. By separating tool-induced distortions from actual process variations, the system enables more precise metrology, reducing false positives in defect detection and improving process control in semiconductor manufacturing. The design clip ensures alignment between the metrology image and the intended wafer design, ensuring accurate distortion compensation.
12. The system of claim 11 , wherein the wafer metrology tool is a scanning electron microscope.
A system for semiconductor wafer inspection includes a wafer metrology tool configured to measure physical characteristics of a semiconductor wafer. The system also includes a processing unit that analyzes the measured data to detect defects or deviations from expected parameters. The wafer metrology tool is a scanning electron microscope (SEM), which provides high-resolution imaging and precise measurements of wafer surface features. The SEM scans the wafer with an electron beam, generating signals that are converted into images or data for analysis. The processing unit processes this data to identify defects such as surface irregularities, contamination, or structural anomalies. The system may also include a positioning mechanism to move the wafer relative to the SEM, ensuring accurate and comprehensive inspection. The SEM's high magnification and resolution capabilities enable detection of sub-micron defects, which are critical for advanced semiconductor manufacturing processes. The system may further include calibration and alignment features to maintain measurement accuracy. The overall system enhances defect detection efficiency, improving yield and reliability in semiconductor production.
13. The system of claim 11 , further comprising an electronic data storage medium containing the design clip, wherein the electronic data storage medium is in electronic communication with the processor.
This invention relates to a system for managing and utilizing design clips, which are reusable design elements or templates. The system addresses the challenge of efficiently storing, retrieving, and applying design clips in digital design workflows, ensuring consistency and reducing redundant work. The system includes a processor configured to generate a design clip from a selected portion of a digital design, where the design clip retains the visual and structural properties of the original design. The processor can also apply the design clip to a new design, adjusting its properties as needed to fit the new context. Additionally, the system may include an electronic data storage medium that stores the design clip and is in electronic communication with the processor, allowing for seamless access and retrieval. The storage medium ensures that design clips are preserved and can be quickly accessed for future use. This system enhances productivity by enabling designers to reuse and modify design elements efficiently, maintaining design consistency across projects.
14. The system of claim 11 , wherein the processor is further configured to perform metrology operations on the synthesized image.
The system relates to image processing and metrology, specifically for analyzing synthesized images to extract precise measurements. The invention addresses the challenge of accurately measuring features in images that are generated or enhanced through computational techniques, where traditional metrology methods may not be directly applicable. The system includes a processor that synthesizes an image by combining or transforming input data, such as multiple sensor readings or different imaging modalities, into a single coherent image. This synthesized image is then subjected to metrology operations, which involve analyzing the image to determine dimensions, distances, angles, or other quantitative properties of the features within it. The metrology operations may include edge detection, pattern recognition, or other image analysis techniques to ensure high precision in the measurements. The system is particularly useful in fields like semiconductor manufacturing, medical imaging, or quality control, where accurate measurements of synthesized or enhanced images are critical for decision-making. By integrating metrology directly into the image synthesis process, the system improves the reliability and accuracy of measurements derived from computationally generated images.
15. The system of claim 11 , wherein the design clip is a synthesized design clip, and wherein the system includes a machine learning module that is configured to: receive images and data from one or more process modulated wafers; learn the process change variations using the images and data; and generate the synthesized design clip using the process change variations.
This invention relates to semiconductor manufacturing, specifically improving process control by generating synthesized design clips to analyze process variations. The system addresses the challenge of detecting and correcting process deviations in semiconductor fabrication, where small variations can significantly impact yield and performance. The system includes a machine learning module that processes images and data from wafers subjected to different fabrication processes. By analyzing these inputs, the module learns how process changes affect the wafer, capturing variations in parameters like etch rates, deposition thickness, or lithography alignment. Using this learned data, the system generates synthesized design clips—simulated representations of design patterns under different process conditions. These clips help predict how real-world process variations will manifest, enabling early detection of defects and optimization of fabrication steps. The synthesized clips can be used for virtual testing, reducing the need for physical wafer testing and accelerating process development. The system integrates with existing semiconductor manufacturing tools, providing a feedback loop to refine process parameters dynamically. This approach enhances yield, reduces waste, and improves the overall efficiency of semiconductor production.
16. A non-transitory computer-readable storage medium, comprising one or more programs for executing the following steps on one or more computing devices: applying a design clip to a metrology area image using an image comparison and rendering process thereby obtaining a synthesized image, wherein one or more process change variations are suppressed and one or more tool distortions are enhanced, wherein the metrology area image is a microscopy image of the wafer, and wherein the design clip includes one or more design polygons and corresponds to an area of the wafer in the metrology area image; and sending instructions to perform metrology operations on the synthesized image.
This invention relates to semiconductor wafer metrology, specifically improving the accuracy of metrology operations by enhancing relevant features in microscopy images. The problem addressed is the difficulty in accurately measuring critical dimensions or detecting defects in wafer images due to process variations and tool-induced distortions that obscure important features. The solution involves a computer-implemented method that processes microscopy images of wafer surfaces. A design clip, containing design polygons corresponding to the wafer area in the image, is applied to the microscopy image using an image comparison and rendering process. This process suppresses unwanted process variations (e.g., random noise or systematic deviations) while enhancing tool distortions (e.g., lens aberrations or alignment errors) that may affect measurement accuracy. The result is a synthesized image where relevant features are more distinguishable. The system then sends instructions to perform metrology operations on this enhanced image, improving the reliability of measurements or defect detection. The method ensures that the metrology process focuses on the most critical aspects of the wafer's structure, reducing errors caused by extraneous variations.
17. The non-transitory computer-readable storage medium of claim 16 , wherein the design clip is a synthesized design clip, and wherein the steps include generating the synthesized design clip using the process change variations with a machine algorithm.
This invention relates to computer-aided design (CAD) and manufacturing, specifically addressing the challenge of generating accurate design clips for process change variations in manufacturing workflows. The invention involves a non-transitory computer-readable storage medium containing instructions that, when executed, perform steps to create a synthesized design clip. The synthesized design clip is generated using process change variations, which are modifications or adjustments made to a manufacturing process to optimize performance, reduce defects, or improve efficiency. A machine algorithm, such as an artificial intelligence or machine learning model, processes these variations to produce the design clip. The design clip serves as a reference or template for implementing the process changes in the manufacturing workflow. The machine algorithm may analyze historical data, simulation results, or real-time feedback to determine the optimal process variations and generate a corresponding design clip. This approach ensures that the design clip accurately reflects the intended process changes, improving consistency and reducing errors in manufacturing operations. The invention enhances automation in design and manufacturing by leveraging machine learning to adapt designs dynamically based on process variations.
18. The non-transitory computer-readable storage medium of claim 17 , wherein the machine algorithm is a deep learning algorithm.
A system and method for processing data using machine learning techniques, particularly deep learning, to improve accuracy and efficiency in data analysis tasks. The invention addresses the challenge of optimizing machine learning models for specific applications by dynamically adjusting algorithm parameters based on input data characteristics. The system includes a data processing module that receives input data and a machine learning module that applies a deep learning algorithm to analyze the data. The deep learning algorithm is configured to adapt its structure or parameters during operation to enhance performance. The system further includes a feedback mechanism that evaluates the algorithm's output and adjusts the model in real-time to improve accuracy. The invention is designed for applications where traditional machine learning models may struggle with complex or high-dimensional data, such as image recognition, natural language processing, or predictive analytics. By leveraging deep learning, the system achieves higher accuracy and adaptability compared to static machine learning models. The non-transitory computer-readable storage medium stores instructions for executing the deep learning algorithm, ensuring reproducibility and scalability of the solution.
19. The non-transitory computer-readable storage medium of claim 16 , wherein the metrology area image is a scanning electron microscope image.
The invention relates to a system for analyzing metrology areas in semiconductor manufacturing, specifically using scanning electron microscope (SEM) images to improve defect detection and classification. The system captures high-resolution SEM images of metrology areas on semiconductor wafers, where these areas are regions designated for process control measurements. The SEM images are processed to identify defects, such as particles, scratches, or pattern deviations, by comparing them against reference images or predefined defect criteria. The system then classifies the detected defects based on their characteristics, such as size, shape, or location, to determine their potential impact on device performance. Additionally, the system may correlate defect data with process parameters to identify root causes and optimize manufacturing processes. By using SEM imaging, the system achieves higher resolution and contrast compared to optical microscopy, enabling the detection of smaller and more subtle defects. The invention improves yield and reliability in semiconductor fabrication by providing detailed defect analysis and actionable insights for process adjustments.
20. The non-transitory computer-readable storage medium of claim 16 , wherein the metrology area image is an average of a plurality of scanning electron microscope images.
A system and method for improving metrology in semiconductor manufacturing involves capturing and processing images of a metrology area using a scanning electron microscope (SEM). The system addresses challenges in accurately measuring critical dimensions and detecting defects in semiconductor wafers, where traditional imaging techniques may suffer from noise, low resolution, or insufficient detail. The invention enhances image quality by averaging multiple SEM images of the same metrology area to reduce noise and improve clarity. This averaging process involves capturing several SEM images under consistent conditions and computationally combining them to produce a final metrology image with higher signal-to-noise ratio and sharper features. The system may also include preprocessing steps such as alignment and normalization to ensure accurate averaging. The resulting high-quality image is then used for precise measurements, defect detection, or process monitoring in semiconductor fabrication. This approach improves the reliability and accuracy of metrology operations, supporting better yield and performance in semiconductor manufacturing.
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April 27, 2018
January 7, 2020
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