A semiconductor device includes a semiconductor substrate, and a semiconductor layer disposed on the semiconductor substrate. First and second pillar layers, of respective first and second conductivity types, are alternately provided in a direction in parallel with a main surface in an active region of the semiconductor layer and in a termination region. A pillar pitch in the termination region is set to be larger than a pillar pitch in the active region. A product of a width of one of the first pillar layers and effective impurity concentration of the first conductivity of the one of the first pillar layers is equal to a product of a width of one of the second pillar layers and effective impurity concentration of the second conductivity of the one of the second pillar layers.
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1. A semiconductor device comprising: a semiconductor substrate; a semiconductor layer of a first conductivity type that is disposed on the semiconductor substrate; a first impurity region of a second conductivity type that is selectively disposed on an upper layer portion of the semiconductor layer in an active region; a second impurity region of the first conductivity type that is selectively disposed on an upper layer portion of the first impurity region; a first main electrode connected to the second impurity region; a gate insulating film disposed to be continuously in contact with the second impurity region, the first impurity region, and the semiconductor layer; a gate electrode disposed to be opposed to the second impurity region, the first impurity region, and the semiconductor layer across the gate insulating film; and a second main electrode disposed on an opposite side to the semiconductor layer of the semiconductor substrate, wherein the semiconductor layer comprises first pillar layers of the first conductivity type and second pillar layers of the second conductivity type, the first pillar layers and the second pillar layers being provided to extend from a main surface located on an opposite side to the semiconductor substrate toward the semiconductor substrate by a predetermined depth, the first pillar layers and the second pillar layers are alternately provided in a direction in parallel with the main surface in the active region of the semiconductor layer and in a termination region that is a region around the active region, the first impurity region is provided in an upper layer portion of the second pillar layers, the semiconductor layer to which the gate insulating film comes in contact is the first pillar layers, a pillar pitch defined by a total width of a pair of one of the first pillar layers and one of the second pillar layers in the termination region is set to be larger than a pillar pitch defined by a total width of a pair of one of the first pillar layers and one of the second pillar layers in the active region, and a product of a width of one of the first pillar layers and effective impurity concentration of the first conductivity of the one of the first pillar layers is equal to a product of a width of one of the second pillar layers and effective impurity concentration of the second conductivity of the one of the second pillar layers in each of the active region and the termination region.
This invention relates to a semiconductor device, specifically a power semiconductor device with a superjunction structure designed to improve breakdown voltage and reduce on-resistance. The device includes a semiconductor substrate with a semiconductor layer of a first conductivity type (e.g., n-type) on top. Within this layer, first and second pillar layers of alternating conductivity types (e.g., n-type and p-type) extend vertically from the surface toward the substrate. These pillars are arranged in both an active region (where current flows) and a termination region (surrounding the active region). The termination region has a larger pillar pitch (distance between adjacent pillars) than the active region to manage electric field distribution and prevent breakdown at the device edges. The device features a first impurity region of a second conductivity type (e.g., p-type) selectively placed on the upper portion of the second pillar layers in the active region, and a second impurity region of the first conductivity type (e.g., n-type) on top of the first impurity region. A gate insulating film contacts the second impurity region, first impurity region, and first pillar layers, with a gate electrode opposite these regions across the insulating film. A first main electrode connects to the second impurity region, while a second main electrode is on the opposite side of the substrate. The design ensures that the product of the width and effective impurity concentration of the first and second pillar layers is equal in both regions, balancing charge to optimize performance. This structure enhances breakdown voltage while maintaining low on-resistance, making it suitable for high-voltage power applications.
2. The semiconductor device according to claim 1 , wherein impurity concentration of the first pillar layers in the active region and impurity concentration of the first pillar layers in the termination region are set to be equal, and impurity concentration of the second pillar layers in the active region and impurity concentration of the second pillar layers in the termination region are set to be equal.
A semiconductor device includes a structure with alternating first and second pillar layers in both an active region and a termination region. The first pillar layers in the active region and the termination region have equal impurity concentrations, and the second pillar layers in the active region and the termination region also have equal impurity concentrations. This design ensures uniform electrical properties across the device, improving reliability and performance. The active region is where the primary semiconductor operations occur, while the termination region surrounds the active region to manage electric field distribution and prevent breakdown. By maintaining consistent impurity levels in corresponding pillar layers across both regions, the device achieves balanced charge carrier behavior and reduces the risk of localized defects or performance degradation. This configuration is particularly useful in power semiconductor devices, where uniform doping profiles are critical for maintaining high breakdown voltages and efficient switching characteristics. The equal impurity concentrations in the pillar layers help maintain consistent electrical properties, ensuring reliable operation under varying voltage and current conditions.
3. The semiconductor device according to claim 1 , wherein the first pillar layers and the second pillar layers are provided by forming the second pillar layers at intervals in the semiconductor layer, below the first pillar layers and the second pillar layers, the semiconductor layer is present as a buffer layer, and a sum of a product of a width of one of the first pillar layers, a depth of the one of the first pillar layers, and effective impurity concentration of the first conductivity of the one of the first pillar layers and a product of one pillar pitch, a thickness of the buffer layer, and impurity concentration of the first conductivity of the buffer layer is equal to a product of a width of one of the second pillar layers, a depth of the one of the second pillar layers, and effective impurity concentration of the second conductivity of the one of the second pillar layers.
This invention relates to semiconductor devices, specifically those with pillar structures for improved electrical performance. The device includes first and second pillar layers formed in a semiconductor layer, with the second pillar layers spaced apart below the first pillar layers. The semiconductor layer beneath these pillars acts as a buffer layer. The key innovation lies in the specific doping configuration, where the sum of two products is equal to a third product. The first product combines the width, depth, and effective impurity concentration of a first pillar layer (of a first conductivity type). The second product combines the pillar pitch, buffer layer thickness, and impurity concentration of the buffer layer (also of the first conductivity type). This sum equals the product of the width, depth, and effective impurity concentration of a second pillar layer (of a second conductivity type). This balanced doping structure optimizes charge carrier distribution, reducing leakage current and improving device efficiency. The buffer layer provides mechanical and electrical stability while maintaining precise control over the electrical properties of the pillar layers. This design is particularly useful in power semiconductor devices where minimizing conduction losses and maximizing breakdown voltage are critical.
4. The semiconductor device according to claim 1 , wherein the semiconductor layer further comprises a RESURF region of the second conductivity type that is provided to extend over upper layer portions of the first pillar layers and the second pillar layers in the termination region, the RESURF region is electrically connected to the first main electrode, and the second pillar layers in the termination region are electrically connected to the first main electrode via the RESURF region.
This invention relates to semiconductor devices, specifically power semiconductor devices with pillar structures, addressing the challenge of improving breakdown voltage and reducing on-resistance in termination regions. The device includes a semiconductor layer with alternating first and second pillar layers of different conductivity types, forming a superjunction structure. In the termination region, the second pillar layers are electrically connected to a first main electrode through a RESURF (Reduced Surface Field) region of the second conductivity type. This RESURF region extends over upper portions of both the first and second pillar layers in the termination region, ensuring uniform potential distribution and minimizing electric field concentration. The RESURF region's connection to the first main electrode facilitates charge balancing, enhancing breakdown voltage while maintaining low on-resistance. The design optimizes the termination region's performance by integrating the RESURF region with the existing pillar structure, preventing premature breakdown and improving overall device reliability. The invention is particularly useful in high-voltage semiconductor applications where efficient termination regions are critical for device performance.
5. The semiconductor device according to claim 4 , wherein the RESURF region is provided to extend up to an outermost periphery of the termination region, and the first pillar layers and the second pillar layers are absent below the RESURF region on the outermost periphery of the termination region.
This invention relates to semiconductor devices, specifically power semiconductor devices with improved breakdown voltage and reliability. The device includes a termination region surrounding an active region, where the termination region contains a RESURF (Reduced Surface Field) region to enhance voltage blocking capability. The RESURF region extends to the outermost edge of the termination region, ensuring uniform electric field distribution and preventing premature breakdown. The termination region also includes alternating first and second pillar layers, which are semiconductor regions with different conductivity types or doping levels, forming a charge-balancing structure to further improve voltage handling. However, these pillar layers are absent directly below the RESURF region at the outermost periphery of the termination region. This design prevents charge imbalance at the edge, reducing leakage current and enhancing device robustness. The absence of pillar layers in this specific area ensures that the RESURF region can effectively manage electric field distribution without interference from the pillar structure, leading to a more reliable semiconductor device with higher breakdown voltage and lower leakage. The invention is particularly useful in high-voltage applications where edge termination reliability is critical.
6. The semiconductor device according to claim 1 , wherein the first pillar layers and the second pillar layers in the termination region are set such that the pillar pitches of the first pillar layers and the second pillar layers have the same value in the entire termination region.
This invention relates to semiconductor devices, specifically those with pillar structures in a termination region designed to improve electrical performance and reliability. The problem addressed is the need for uniform electric field distribution in the termination region of semiconductor devices, which is critical for preventing breakdown and ensuring reliable operation. The semiconductor device includes a termination region with first and second pillar layers arranged in a specific pattern. The first pillar layers are formed in a semiconductor substrate, while the second pillar layers are formed on the first pillar layers. The key innovation is that the pillar pitches (the spacing between adjacent pillars) of both the first and second pillar layers are set to the same value throughout the entire termination region. This uniform pitch distribution helps achieve a balanced electric field, reducing the risk of localized high-field regions that could lead to device failure. The termination region surrounds an active region where the primary semiconductor functions occur, such as in power devices like MOSFETs or IGBTs. By maintaining consistent pillar spacing, the device can better manage voltage distribution, particularly during high-voltage operation. This design minimizes edge effects and enhances the device's robustness against electrical stress. The uniform pitch also simplifies manufacturing, as it avoids complex variations in pillar spacing that could complicate fabrication processes. Overall, the invention provides a reliable and manufacturable solution for improving the performance of semiconductor devices in high-voltage applications.
7. The semiconductor device according to claim 1 , wherein the first pillar layers and the second pillar layers in the termination region are set such that a pillar pitch defined by a total width of a pair of one of the first pillar layers and one of the second pillar layers that are provide in a region close to the active region and a pillar pitch of another of the first pillar layers and another of the second pillar layers have different values.
This invention relates to semiconductor devices, specifically addressing the design of termination regions in semiconductor structures to improve performance and reliability. The problem being solved involves optimizing the arrangement of pillar layers in the termination region to manage electric field distribution and reduce leakage current, which is critical for high-voltage semiconductor devices. The semiconductor device includes an active region and a termination region surrounding the active region. The termination region contains first pillar layers and second pillar layers, which are conductive or insulating structures that influence the electric field distribution. The key innovation is that the spacing (pillar pitch) between adjacent first and second pillar layers varies depending on their proximity to the active region. Specifically, the pitch between a pair of first and second pillar layers closest to the active region differs from the pitch between other pairs of first and second pillar layers further away. This variable pitch design helps to gradually distribute the electric field, preventing field crowding and improving breakdown voltage characteristics. The first pillar layers and second pillar layers may be doped regions, trenches, or other structural features that contribute to electric field management. By adjusting the pitch, the device achieves better termination performance, reducing leakage and enhancing reliability in high-voltage applications. This approach is particularly useful in power semiconductor devices where efficient electric field control is essential.
8. The semiconductor device according to claim 1 , wherein the semiconductor substrate uses silicon carbide as a semiconductor.
This technical summary describes a semiconductor device incorporating silicon carbide (SiC) as the semiconductor material. The device addresses the limitations of traditional silicon-based semiconductors, such as lower thermal conductivity and breakdown voltage, by leveraging the superior properties of SiC, including higher thermal stability, higher electron mobility, and greater resistance to high-voltage and high-temperature environments. This makes the device particularly suitable for high-power, high-frequency, and high-temperature applications, such as power electronics, electric vehicles, and renewable energy systems. The semiconductor device includes a semiconductor substrate, which is the foundational layer for the device's active components. The substrate is composed of silicon carbide, providing enhanced electrical and thermal performance compared to silicon. The device may also include additional layers or structures, such as insulating layers, conductive layers, or doped regions, to form transistors, diodes, or other semiconductor components. These components are integrated into the SiC substrate to enable efficient switching, rectification, or signal processing in demanding operating conditions. By using silicon carbide, the device achieves improved efficiency, reduced power loss, and increased reliability in harsh environments, making it a critical advancement for modern power electronics and high-performance semiconductor applications.
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June 2, 2017
January 7, 2020
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