The present disclosure relates to semiconductor structures and, more particularly, to electrostatic discharge structures with reduced capacitance and methods of manufacture. The structure includes: a plurality of fin structures provided in at least one N+ type region and at least one P+ region; and a plurality of gate structures disposed over the plurality of fin structures and within the at least one N+ type region and one P+ region, the plurality of gate structures being separated in a lengthwise direction between the at least one N+ type region and the least one P+ region.
Legal claims defining the scope of protection, as filed with the USPTO.
1. An electrostatic discharge structure, comprising: a plurality of fin structures provided in at least one N+ type region and at least one P+ region; and a plurality of gate structures disposed over the plurality of fin structures and within the at least one N+ type region and one P+ region, the plurality of gate structures being separated in a lengthwise direction between the at least one N+ type region and the least one P+ region, wherein the at least one N+ type region and at least one P+ region comprise N+ type epitaxial material and P+ type epitaxial material deposited over the plurality of gate structures in the at least one N+ type region and in the at least one P+ region respectively; wherein the plurality of gate structures disposed over the plurality of fin structures comprise a transverse cut which separates them along the lengthwise direction, the transverse cut being located between the N+ type epitaxial material and P+ type epitaxial material and over the shallow trench isolation features, with the ends of the plurality of gate structures being in alignment in each respective region.
2. The structure of claim 1 , wherein the plurality of gate structures are cut transversely to maintain a separation between the gate structures in the lengthwise direction and between at least one N+ type region and the least one P+ type region.
3. The structure of claim 2 , wherein the plurality of gate structures include multiple gate structures over each of the at least one N+ type region and the at least one P+ type region, wherein ends of the multiple gate structures are aligned and separated from each along the lengthwise direction.
4. The structure of claim 1 , wherein the fin structures are composed of semiconductor material.
5. The structure of claim 1 , wherein the at least one N+ region is two N+ regions adjacent to the at least one P+ region.
6. The structure of claim 5 , wherein the two N+ regions and the at least one P+ region are epitaxial material with N+ doping and P+ doping, respectively.
7. The structure of claim 5 , wherein the separation of the plurality of gate structures in the lengthwise direction between the at least one N+ type region and the least one P+ region disrupts a capacitance pathway.
8. The structure of claim 1 , wherein the at least one P+ region is two P+ regions adjacent to the at least one N+ region.
9. An electrostatic discharge structure, comprising: a first region of a first dopant type extending over a plurality of fin structures; a second region of a second dopant extending over the plurality of fin structures and adjacent to the first region; a third region of the first dopant type extending over the plurality of fin structures and adjacent to the second region; a first plurality of gate structures in the first region; a second plurality of gate structures in the second region; and a third plurality of gate structures in the third region, wherein the first plurality of gate structures, the second plurality of gate structures and the third plurality of gate structures are separated in a lengthwise direction, and wherein the first dopant type is a first doped epitaxial material deposited over the plurality of fin structures and the first plurality of gate structures in the first region and the third plurality of gate structures in the third region, and wherein the second dopant type is a second doped epitaxial material deposited over the plurality of fin structures and the second plurality of gate structures in the second region; wherein the first, second and third plurality of gate structures are each cut along the lengthwise direction so as to separate from one another each of the first, second and third plurality of gate structures, the cuts are located (i) between the first doped epitaxial material deposited over the first plurality of gate structures in the first region and the second doped epitaxial material deposited over the second plurality of gate structures in the second region and (ii) between the first doped epitaxial material deposited over the third plurality of gate structures in the third region and the second doped epitaxial material deposited over the second plurality of gate structures in the second region, and the cuts are further provided over shallow trench isolation regions which are devoid of the first doped epitaxial material and the second doped epitaxial material.
10. The structure of claim 9 , wherein the first region and the third region are N+ type regions and the second region is a P+ type region.
11. The structure of claim 9 , wherein the first region and the third region are P+ type regions and the second region is a N+ type region.
12. The structure of claim 9 , wherein individual gate structures of the first plurality of gate structures, the second plurality of gate structures and the third plurality of gate structures are each aligned end to end.
13. The structure of claim 9 , wherein the separation of the plurality of gate structures in the lengthwise direction disrupts a capacitance pathway.
14. The structure of claim 13 , wherein the capacitance pathway is between the gate structures and two differently doped regions.
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June 26, 2018
January 21, 2020
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