Systems and methods provide, as part of an executable graphical model, a region for providing variants that includes one or more computational choices defining alternative execution implementations of the region. Conditions assigned to the one or more computational choices indicate which of the computational choices is active. The conditions specify logical expressions of variables that evaluate to True or False. For a given simulation of the executable graphical model, all of the logical expressions may evaluate to False, such that none of the computational choices are active. All of the computational choices of the executable graphical model may be removed for the given simulation.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A computer-implemented method comprising: providing, as part of a graphical model having executable semantics, a region for providing variants, the region including one or more computational choices that define alternative execution implementations of the region, and one or more conditions assigned to the one or more computational choices, the one or more conditions indicating which one of the one or more computational choices is active, where the one or more conditions assigned to the one or more computational choices specify one or more logical expressions of one or more variables for controlling activation of the one or more computational choices, and the one or more logical expressions evaluate to either an asserted value or a de-asserted value based on a given value of the one or more variables; propagating, by one or more processors, the one or more conditions to model elements included in the one or more computational choices; evaluating, by the one or more processors, the one or more logical expressions specified for the one or more conditions; and for a given execution of the graphical model or a given generation of code for the graphical model, determining that the one or more logical expressions specified for all of the one or more conditions evaluate to the de-asserted value.
2. The computer-implemented method of claim 1 wherein the asserted value is True and the de-asserted value is False.
3. The computer-implemented method of claim 1 wherein the region includes only a single computational choice.
4. The computer-implemented method of claim 3 wherein the single computational choice is implemented through at least one of a variant source block, a variant sink block, a variant start block, a variant end block, or a variant subsystem block.
5. The computer-implemented method of claim 1 wherein the region includes a plurality of computational choices.
6. The computer-implemented method of claim 5 wherein the plurality of computational choices are implemented through at least one of a variant source block, a variant sink block, a variant start block, a variant end block, or a variant subsystem block.
7. The computer-implemented method of claim 1 wherein the model elements include two or more model elements coupled by a non-signal boundary, and the propagating is performed along the non-signal boundary.
8. The computer-implemented method of claim 7 wherein at least one of the two or more model elements is a data store block, a callee function block, a caller function block, an initialize subsystem block, a reset subsystem block, or a terminate subsystem block.
9. The computer-implemented method of claim 1 wherein at least one of the model elements is a subsystem block or a model block representing a hierarchical layer of the graphical model, and the propagating is performed through the hierarchical layer.
10. The computer-implemented method of claim 1 further comprising: removing from the region of the graphical model the one or more computational choices in response to the one or more logical expressions for all of the one or more conditions evaluating to the de-asserted value.
11. One or more non-transitory computer-readable media, having stored thereon instructions that when executed by a computing device, cause the computing device to perform operations comprising: provide, as part of a graphical model having executable semantics, a region for providing variants, the region including one or more computational choices that define alternative execution implementations of the region, and one or more conditions assigned to the one or more computational choices, the one or more conditions indicating which one of the one or more computational choices is active, where the one or more conditions assigned to the one or more computational choices specify one or more logical expressions of one or more variables for controlling activation of the one or more computational choices, and the one or more logical expressions evaluate to either an asserted value or a de-asserted value based on a given value of the one or more variables; propagate, by one or more processors, the one or more conditions to model elements included in the one or more computational choices; evaluate, by the one or more processors, the one or more logical expressions specified for the one or more conditions; and for a given execution of the graphical model or a given generation of code for the graphical model, determine that the one or more logical expressions specified for all of the one or more conditions evaluate to the de-asserted value.
12. The one or more non-transitory computer-readable media of claim 11 wherein the asserted value is True and the de-asserted value is False.
13. The one or more non-transitory computer-readable media of claim 11 wherein the region includes only a single computational choice, and the single computational choice is implemented through at least one of a variant source block, a variant sink block, a variant start block, a variant end block, or a variant subsystem block.
14. The one or more non-transitory computer-readable media of claim 11 wherein the region includes a plurality of computational choices, and the plurality of computational choices are implemented through at least one of a variant source block, a variant sink block, a variant start block, a variant end block, or a variant subsystem block.
15. The one or more non-transitory computer-readable media of claim 11 wherein the model elements include two or more model elements coupled by a non-signal boundary, and the propagating is performed along the non-signal boundary.
16. The one or more non-transitory computer-readable media of claim 15 wherein at least one of the two or more model elements is a data store block, a callee function block, a caller function block, an initialize subsystem block, a reset subsystem block, or a terminate subsystem block.
17. The one or more non-transitory computer-readable media of claim 11 wherein at least one of the model elements is a subsystem block or a model block representing a hierarchical layer of the graphical model, and the propagating is performed through the hierarchical layer.
18. The one or more non-transitory computer-readable media of claim 11 wherein the operations further comprise: remove from the region of the graphical model the one or more computational choices in response to the one or more logical expressions for all of the one or more conditions evaluating to the de-asserted value.
19. An apparatus comprising: a memory configured to store a graphical model having executable semantics, the graphical model including a region for providing variants, the region including one or more computational choices that define alternative execution implementations of the region, and one or more conditions assigned to the one or more computational choices, the one or more conditions indicating which one of the one or more computational choices is active, where the one or more conditions assigned to the one or more computational choices specify one or more logical expressions of one or more variables for controlling activation of the one or more computational choices, and the one or more logical expressions evaluate to either an asserted value or a de-asserted value based on a given value of the one or more variables; and one or more processors coupled to the memory, the one or more processors configured to: propagate the one or more conditions to model elements included in the one or more computational choices; evaluate the one or more logical expressions specified for the one or more conditions; and for a given execution of the graphical model or a given generation of code for the graphical model, determine that the one or more logical expressions specified for all of the one or more conditions evaluate to the de-asserted value.
20. The apparatus of claim 19 wherein the region includes only a single computational choice, and the single computational choice is implemented through at least one of a variant source block, a variant sink block, a variant start block, a variant end block, or a variant subsystem block.
21. The apparatus of claim 19 wherein the region includes a plurality of computational choices, and the plurality of computational choices are implemented through at least one of a variant source block, a variant sink block, a variant start block, a variant end block, or a variant subsystem block.
22. The apparatus of claim 19 wherein the model elements include two or more model elements coupled by a non-signal boundary, and the propagating is performed along the non-signal boundary.
23. The apparatus of claim 22 wherein at least one of the two or more model elements is a data store block, a callee function block, a caller function block, an initialize subsystem block, a reset subsystem block, or a terminate subsystem block.
24. The apparatus of claim 19 wherein at least one of the model elements is a subsystem block or a model block representing a hierarchical layer of the graphical model, and the propagating is performed through the hierarchical layer.
25. The apparatus of claim 19 wherein the operations further comprise: remove from the region of the graphical model the one or more computational choices in response to the one or more logical expressions for all of the one or more conditions evaluating to the de-asserted value.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
December 1, 2017
January 28, 2020
Browse 5M+ US patents with plain-English claim translations and AI-generated analysis.