Semiconductor memory device including a capacitor

1. A nonvolatile memory device comprising: a memory cell array formed in a first area of a substrate; and a page buffer circuit formed in a second area of the substrate and connected to the memory cell array through bit lines, wherein the memory cell array comprises cell strings, each of the cell strings comprising nonvolatile memory cells stacked in a direction perpendicular to the substrate, wherein the page buffer circuit comprises page buffers respectively corresponding to the bit lines, wherein each of the page buffers comprises latches connected to a sensing node, and a selection circuit configured to selectively connect the sensing node to a corresponding bit line of the bit lines, wherein at least one latch of the latches comprises a capacitor configured to selectively store a voltage of the sensing node, wherein the capacitor comprises at least one first contact to which the voltage of the sensing node is selectively supplied, the at least one first contact having a second height corresponding to a first height of each of the cell strings, and at least one second contact to which a ground voltage is supplied, the at least one second contact having a third height corresponding to the first height, disposed adjacent to the at least one first contact, and electrically separated from the at least one first contact, wherein the at least one first contact includes two or more first contacts, and the capacitor further comprises a conductive pattern connecting the two or more first contacts, and wherein the conductive pattern is disposed on upper surfaces of the two or more first contacts.

2. The nonvolatile memory device of claim 1 , wherein the conductive pattern, and an insulating material insulating the conductive pattern from the substrate, are disposed between lower surfaces of the two or more first contacts and the substrate.

3. A nonvolatile memory device comprising: a memory cell array formed in a first area of a substrate; and a page buffer circuit formed in a second area of the substrate and connected to the memory cell array through bit lines, wherein the memory cell array comprises cell strings, each of the cell strings comprising nonvolatile memory cells stacked in a direction perpendicular to the substrate, wherein the page buffer circuit comprises page buffers respectively corresponding to the bit lines, wherein each of the page buffers comprises latches connected to a sensing node, and a selection circuit configured to selectively connect the sensing node to a corresponding bit line of the bit lines, wherein at least one latch of the latches comprises a capacitor configured to selectively store a voltage of the sensing node, wherein the capacitor comprises at least one first contact to which the voltage of the sensing node is selectively supplied, the at least one first contact having a second height corresponding to a first height of each of the cell strings, and at least one second contact to which a ground voltage is supplied, the at least one second contact having a third height corresponding to the first height, disposed adjacent to the at least one first contact, and electrically separated from the at least one first contact, wherein the at least one first contact includes two or more first contacts, and the capacitor further comprises a conductive pattern connecting the two or more first contacts, wherein the at least one second contact includes two or more second contacts, wherein a first conductive pattern connecting the two or more second contacts is disposed on upper surfaces of the two or more second contacts, and wherein a second conductive pattern connecting the two or more second contacts, and an insulating material insulating the second conductive pattern from the substrate, are disposed between lower surfaces of the two or more second contacts and the substrate.

4. The nonvolatile memory device of claim 1 , wherein the capacitor further comprises: at least one third contact disposed at a first side of the at least one first contact, which is opposite to a second side of the at least one first contact which faces the at least one second contact.

5. A nonvolatile memory device comprising: a memory cell array formed in a first area of a substrate; and a page buffer circuit formed in a second area of the substrate and connected to the memory cell array through bit lines, wherein the memory cell array comprises cell strings, each of the cell strings comprising nonvolatile memory cells stacked in a direction perpendicular to the substrate, wherein the page buffer circuit comprises page buffers respectively corresponding to the bit lines, wherein each of the page buffers comprises latches connected to a sensing node, and a selection circuit configured to selectively connect the sensing node to a corresponding bit line of the bit lines, wherein at least one latch of the latches comprises a capacitor configured to selectively store a voltage of the sensing node, wherein the capacitor comprises at least one first contact to which the voltage of the sensing node is selectively supplied, the at least one first contact having a second height corresponding to a first height of each of the cell strings, and at least one second contact to which a ground voltage is supplied, the at least one second contact having a third height corresponding to the first height, disposed adjacent to the at least one first contact, and electrically separated from the at least one first contact, wherein the at least one first contact includes two or more first contacts, and the capacitor further comprises a conductive pattern connecting the two or more first contacts, wherein the capacitor further comprises at least one third contact disposed at a first side of the at least one first contact, which is opposite to a second side of the at least one first contact which faces the at least one second contact, and wherein another conductive pattern connecting the at least one second contact and the at least one third contact is disposed over the at least one first contact, the at least one second contact, and the at least one third contact.

6. The nonvolatile memory device of claim 4 , wherein a first junction electrically connecting the at least one second contact and the at least one third contact is disposed in the substrate, and wherein the at least one first contact is disposed on an insulating material disposed on the first junction.

7. The nonvolatile memory device of claim 6 , wherein second junctions having a doping concentration higher than a doping concentration of the first junction are respectively disposed in a first portion of the first junction, which is in contact with the at least one second contact, and in a second portion of the first junction which is in contact with the at least one third contact.

8. The nonvolatile memory device of claim 4 , wherein the at least one third contact is connected to another conductive pattern configured to supply power to the latches of each of the page buffers.

9. The nonvolatile memory device of claim 4 , wherein the capacitor further comprises at least one fourth contact and at least one fifth contact disposed at respective sides of the at least one first contact other than the first and second sides of the at least one first contact.

10. The nonvolatile memory device of claim 9 , wherein the at least one second contact comprises: two or more second contacts disposed in line from a first location close to a location where the at least one fourth contact is disposed, to a second location adjacent to a location where the at least one fifth contact is disposed.

11. The nonvolatile memory device of claim 9 , wherein the capacitor further comprises at least one sixth contact, at least one seventh contact, at least one eighth contact, and at least one ninth contact respectively disposed at locations corresponding to corners of the at least one first contact in diagonal directions.