At least one latch of a page buffer of a nonvolatile memory device includes a capacitor that selectively stores a voltage of a sensing node. The capacitor includes at least one first contact having a second height corresponding to a first height of each of cell strings, and at least one second contact to which a ground voltage is supplied. The at least one second contact has a third height corresponding to the first height, disposed adjacent to the at least one first contact, and electrically separated from the at least one first contact.
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1. A nonvolatile memory device comprising: a memory cell array formed in a first area of a substrate; and a page buffer circuit formed in a second area of the substrate and connected to the memory cell array through bit lines, wherein the memory cell array comprises cell strings, each of the cell strings comprising nonvolatile memory cells stacked in a direction perpendicular to the substrate, wherein the page buffer circuit comprises page buffers respectively corresponding to the bit lines, wherein each of the page buffers comprises latches connected to a sensing node, and a selection circuit configured to selectively connect the sensing node to a corresponding bit line of the bit lines, wherein at least one latch of the latches comprises a capacitor configured to selectively store a voltage of the sensing node, wherein the capacitor comprises at least one first contact to which the voltage of the sensing node is selectively supplied, the at least one first contact having a second height corresponding to a first height of each of the cell strings, and at least one second contact to which a ground voltage is supplied, the at least one second contact having a third height corresponding to the first height, disposed adjacent to the at least one first contact, and electrically separated from the at least one first contact, wherein the at least one first contact includes two or more first contacts, and the capacitor further comprises a conductive pattern connecting the two or more first contacts, and wherein the conductive pattern is disposed on upper surfaces of the two or more first contacts.
This invention relates to a nonvolatile memory device, specifically a three-dimensional (3D) NAND flash memory, addressing challenges in integrating high-density memory cells with efficient peripheral circuitry. The device includes a memory cell array formed in a first substrate area and a page buffer circuit in a second area, connected via bit lines. The memory cell array consists of cell strings with nonvolatile memory cells stacked perpendicularly to the substrate, enabling high-density storage. The page buffer circuit contains page buffers corresponding to each bit line, each with latches connected to a sensing node and a selection circuit to selectively connect the sensing node to a bit line. A key innovation is a capacitor within at least one latch, designed to store the sensing node voltage. The capacitor features multiple first contacts, each with a height matching the cell strings, connected by a conductive pattern on their upper surfaces. Adjacent second contacts, also matching the cell string height, supply a ground voltage and are electrically isolated from the first contacts. This design optimizes space utilization and ensures stable voltage storage, improving read/write operations in high-density 3D NAND memory.
2. The nonvolatile memory device of claim 1 , wherein the conductive pattern, and an insulating material insulating the conductive pattern from the substrate, are disposed between lower surfaces of the two or more first contacts and the substrate.
A nonvolatile memory device includes a substrate with a conductive pattern and an insulating material. The conductive pattern is insulated from the substrate by the insulating material. The device further includes two or more first contacts positioned above the conductive pattern and the insulating material. The conductive pattern and the insulating material are disposed between the lower surfaces of the two or more first contacts and the substrate. This configuration allows for improved electrical isolation and reduced interference between the conductive pattern and the substrate, enhancing the performance and reliability of the memory device. The conductive pattern may be used for routing signals or power within the device, while the insulating material prevents unintended electrical coupling. The first contacts provide electrical connections to other components or layers in the memory device. This structure is particularly useful in high-density memory devices where minimizing parasitic effects and ensuring stable operation are critical. The insulating material ensures that the conductive pattern does not interfere with underlying circuitry or the substrate, maintaining signal integrity and device functionality.
3. A nonvolatile memory device comprising: a memory cell array formed in a first area of a substrate; and a page buffer circuit formed in a second area of the substrate and connected to the memory cell array through bit lines, wherein the memory cell array comprises cell strings, each of the cell strings comprising nonvolatile memory cells stacked in a direction perpendicular to the substrate, wherein the page buffer circuit comprises page buffers respectively corresponding to the bit lines, wherein each of the page buffers comprises latches connected to a sensing node, and a selection circuit configured to selectively connect the sensing node to a corresponding bit line of the bit lines, wherein at least one latch of the latches comprises a capacitor configured to selectively store a voltage of the sensing node, wherein the capacitor comprises at least one first contact to which the voltage of the sensing node is selectively supplied, the at least one first contact having a second height corresponding to a first height of each of the cell strings, and at least one second contact to which a ground voltage is supplied, the at least one second contact having a third height corresponding to the first height, disposed adjacent to the at least one first contact, and electrically separated from the at least one first contact, wherein the at least one first contact includes two or more first contacts, and the capacitor further comprises a conductive pattern connecting the two or more first contacts, wherein the at least one second contact includes two or more second contacts, wherein a first conductive pattern connecting the two or more second contacts is disposed on upper surfaces of the two or more second contacts, and wherein a second conductive pattern connecting the two or more second contacts, and an insulating material insulating the second conductive pattern from the substrate, are disposed between lower surfaces of the two or more second contacts and the substrate.
A nonvolatile memory device includes a memory cell array and a page buffer circuit formed on a substrate. The memory cell array is arranged in a first area of the substrate and comprises cell strings of nonvolatile memory cells stacked perpendicularly to the substrate. The page buffer circuit is formed in a second area of the substrate and is connected to the memory cell array through bit lines. The page buffer circuit includes page buffers corresponding to each bit line, with each page buffer containing latches connected to a sensing node and a selection circuit that selectively connects the sensing node to a corresponding bit line. At least one latch in the page buffer includes a capacitor that selectively stores the voltage of the sensing node. The capacitor has at least one first contact to which the sensing node voltage is supplied, with the first contact having a height matching the height of the cell strings. The capacitor also includes at least one second contact, which receives a ground voltage and is electrically isolated from the first contact. The second contact has a height matching the cell string height and is positioned adjacent to the first contact. The first contact consists of multiple contacts connected by a conductive pattern, while the second contact also consists of multiple contacts. The second contacts are connected by a first conductive pattern on their upper surfaces and a second conductive pattern on their lower surfaces, with an insulating material separating the second conductive pattern from the substrate. This design optimizes the capacitor's structure within the memory device, ensuring efficient voltage storage and grounding while maintaining spatial alignment with the memory cell array.
4. The nonvolatile memory device of claim 1 , wherein the capacitor further comprises: at least one third contact disposed at a first side of the at least one first contact, which is opposite to a second side of the at least one first contact which faces the at least one second contact.
Nonvolatile memory devices, such as flash memory, rely on capacitors to store charge and represent data states. A key challenge is optimizing the capacitor structure to improve performance, reliability, and scalability. Traditional designs may suffer from limited charge retention, high leakage, or complex fabrication processes. This invention addresses these issues by enhancing the capacitor structure in a nonvolatile memory device. The capacitor includes a first contact and a second contact, which are positioned to facilitate charge storage and retention. A third contact is added to the capacitor, specifically located on the opposite side of the first contact relative to the second contact. This third contact improves charge distribution, reduces leakage, and enhances overall capacitor efficiency. The placement of the third contact ensures balanced electrical fields and minimizes interference, leading to more stable data storage. The design also simplifies manufacturing by integrating the third contact without requiring significant modifications to existing fabrication processes. This innovation is particularly useful in high-density memory applications where reliability and performance are critical.
5. A nonvolatile memory device comprising: a memory cell array formed in a first area of a substrate; and a page buffer circuit formed in a second area of the substrate and connected to the memory cell array through bit lines, wherein the memory cell array comprises cell strings, each of the cell strings comprising nonvolatile memory cells stacked in a direction perpendicular to the substrate, wherein the page buffer circuit comprises page buffers respectively corresponding to the bit lines, wherein each of the page buffers comprises latches connected to a sensing node, and a selection circuit configured to selectively connect the sensing node to a corresponding bit line of the bit lines, wherein at least one latch of the latches comprises a capacitor configured to selectively store a voltage of the sensing node, wherein the capacitor comprises at least one first contact to which the voltage of the sensing node is selectively supplied, the at least one first contact having a second height corresponding to a first height of each of the cell strings, and at least one second contact to which a ground voltage is supplied, the at least one second contact having a third height corresponding to the first height, disposed adjacent to the at least one first contact, and electrically separated from the at least one first contact, wherein the at least one first contact includes two or more first contacts, and the capacitor further comprises a conductive pattern connecting the two or more first contacts, wherein the capacitor further comprises at least one third contact disposed at a first side of the at least one first contact, which is opposite to a second side of the at least one first contact which faces the at least one second contact, and wherein another conductive pattern connecting the at least one second contact and the at least one third contact is disposed over the at least one first contact, the at least one second contact, and the at least one third contact.
A nonvolatile memory device includes a memory cell array and a page buffer circuit formed on a substrate. The memory cell array contains cell strings of nonvolatile memory cells stacked perpendicularly to the substrate. The page buffer circuit is connected to the memory cell array through bit lines and includes page buffers corresponding to each bit line. Each page buffer has latches connected to a sensing node and a selection circuit that selectively connects the sensing node to a bit line. At least one latch includes a capacitor that stores the voltage of the sensing node. The capacitor has first contacts, which receive the sensing node voltage, and second contacts, which receive a ground voltage. Both types of contacts have heights matching the height of the cell strings. The first contacts are electrically separated from the second contacts and are connected by a conductive pattern. Additionally, the capacitor includes third contacts positioned opposite the second contacts relative to the first contacts. Another conductive pattern connects the second and third contacts, positioned above the first, second, and third contacts. This configuration enhances the capacitor's storage capability while maintaining structural alignment with the memory cell array. The design optimizes space utilization and electrical performance in the nonvolatile memory device.
6. The nonvolatile memory device of claim 4 , wherein a first junction electrically connecting the at least one second contact and the at least one third contact is disposed in the substrate, and wherein the at least one first contact is disposed on an insulating material disposed on the first junction.
This invention relates to a nonvolatile memory device, specifically addressing the structural arrangement of contacts and junctions within the device to improve performance and reliability. The device includes a substrate with a first junction formed therein, which electrically connects at least one second contact and at least one third contact. The first junction is positioned within the substrate, ensuring stable electrical connectivity between these contacts. Additionally, at least one first contact is placed on an insulating material that is disposed over the first junction. This configuration isolates the first contact from the underlying junction, reducing interference and enhancing signal integrity. The insulating material acts as a barrier, preventing direct electrical contact between the first contact and the junction while maintaining the necessary connections between the second and third contacts. This structural design is particularly useful in nonvolatile memory devices where precise control of electrical pathways is critical for data retention and operational efficiency. The arrangement minimizes parasitic effects and improves the overall reliability of the memory device.
7. The nonvolatile memory device of claim 6 , wherein second junctions having a doping concentration higher than a doping concentration of the first junction are respectively disposed in a first portion of the first junction, which is in contact with the at least one second contact, and in a second portion of the first junction which is in contact with the at least one third contact.
This invention relates to nonvolatile memory devices, specifically addressing challenges in optimizing electrical performance and reliability in memory cells. The device includes a first junction with at least one second contact and at least one third contact. To enhance conductivity and reduce resistance, second junctions with higher doping concentrations than the first junction are integrated into specific regions of the first junction. These second junctions are positioned where the first junction interfaces with the second and third contacts, ensuring efficient charge transport and minimizing contact resistance. The higher doping concentration in these localized regions improves the electrical connection between the first junction and the contacts, leading to faster read/write operations and improved endurance. This design is particularly useful in memory cells where low resistance and high reliability are critical, such as in flash memory or other nonvolatile storage technologies. The selective doping approach balances performance and manufacturing complexity, avoiding excessive doping across the entire junction while still achieving the desired electrical properties.
8. The nonvolatile memory device of claim 4 , wherein the at least one third contact is connected to another conductive pattern configured to supply power to the latches of each of the page buffers.
Nonvolatile memory devices, such as flash memory, require efficient power distribution to maintain data integrity and performance. A key challenge is ensuring stable power delivery to page buffers, which contain latches that temporarily store data during read, program, and erase operations. Unstable power supply can lead to data corruption or operational failures. This invention addresses the problem by incorporating at least one additional contact in the nonvolatile memory device. This contact is connected to another conductive pattern specifically designed to supply power to the latches within each page buffer. The conductive pattern ensures a dedicated and reliable power path, reducing voltage fluctuations and improving latch stability. This design minimizes the risk of data errors during memory operations and enhances overall device reliability. The additional contact and conductive pattern work together to provide a robust power distribution network, ensuring consistent performance across the memory array. This solution is particularly useful in high-density memory devices where power integrity is critical for maintaining data accuracy and operational efficiency.
9. The nonvolatile memory device of claim 4 , wherein the capacitor further comprises at least one fourth contact and at least one fifth contact disposed at respective sides of the at least one first contact other than the first and second sides of the at least one first contact.
Nonvolatile memory devices, such as flash memory, often require high-density storage with reliable charge retention. A key challenge is designing capacitors that efficiently store charge while minimizing leakage and maximizing storage density. To address this, a nonvolatile memory device includes a capacitor structure with improved charge retention and reduced leakage. The capacitor comprises a first contact and a second contact disposed on opposite sides of the first contact, forming a primary charge storage region. Additionally, the capacitor includes at least one fourth contact and at least one fifth contact positioned at other sides of the first contact, distinct from the first and second sides. These additional contacts enhance charge distribution and reduce leakage paths, improving overall reliability and performance. The capacitor structure may be integrated into a memory cell, such as a floating-gate or charge-trap cell, to enhance data retention and operational stability. The design ensures efficient charge storage while maintaining compact dimensions, making it suitable for high-density memory applications. This configuration helps mitigate charge loss and improves the longevity of stored data, addressing common reliability issues in nonvolatile memory devices.
10. The nonvolatile memory device of claim 9 , wherein the at least one second contact comprises: two or more second contacts disposed in line from a first location close to a location where the at least one fourth contact is disposed, to a second location adjacent to a location where the at least one fifth contact is disposed.
This invention relates to nonvolatile memory devices, specifically addressing the arrangement of electrical contacts within such devices to improve performance and reliability. The problem being solved involves optimizing the placement and configuration of contacts to enhance signal integrity, reduce interference, and improve data access efficiency in memory cells. The nonvolatile memory device includes a memory cell array with multiple contacts for electrical connections. The device features at least one first contact connected to a bit line, at least one second contact connected to a word line, at least one third contact connected to a source line, at least one fourth contact connected to a control gate, and at least one fifth contact connected to a drain. The invention focuses on the arrangement of the second contacts, which are connected to the word line. These second contacts are positioned in a linear configuration, extending from a first location near the fourth contact (control gate) to a second location adjacent to the fifth contact (drain). The linear arrangement ensures efficient signal routing and minimizes electrical interference, improving the overall performance of the memory device. This configuration helps maintain consistent electrical characteristics across the memory array, reducing errors and enhancing data retention. The invention is particularly useful in high-density memory devices where precise contact placement is critical for reliable operation.
11. The nonvolatile memory device of claim 9 , wherein the capacitor further comprises at least one sixth contact, at least one seventh contact, at least one eighth contact, and at least one ninth contact respectively disposed at locations corresponding to corners of the at least one first contact in diagonal directions.
Nonvolatile memory devices, such as flash memory, often require compact and efficient capacitor structures to store charge reliably. A key challenge is ensuring stable charge retention while minimizing device footprint and manufacturing complexity. This invention addresses these issues by enhancing the capacitor structure in a nonvolatile memory device. The device includes a capacitor with multiple contacts strategically placed to improve performance. Specifically, the capacitor has a first contact and a second contact, where the first contact is positioned at a central location relative to the capacitor. Additionally, the capacitor includes a third contact, a fourth contact, and a fifth contact, each disposed at locations corresponding to corners of the first contact in diagonal directions. These contacts are symmetrically arranged to optimize charge distribution and reduce leakage. Furthermore, the capacitor includes at least one sixth contact, at least one seventh contact, at least one eighth contact, and at least one ninth contact, also positioned at locations corresponding to corners of the first contact in diagonal directions. This additional set of contacts enhances charge retention and stability by providing redundant pathways for charge storage and retrieval. The symmetric placement of these contacts ensures uniform electric field distribution, minimizing stress and improving reliability. This design improves charge retention, reduces leakage, and enhances the overall efficiency of the nonvolatile memory device, making it suitable for high-density storage applications.
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June 3, 2018
January 28, 2020
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