Tensile strain is applied to a channel region of a transistor by depositing an amorphous SixGe1-x-yCy alloy in at least one of a source and a drain (S/D) region of the transistors. The amorphous SixGe1-x-yCy alloy is crystallized, thus reducing the unit volume of the alloy. This volume reduction in at least one of the source and the drain region applies strain to a connected channel region. This strain improves electron mobility in the channel. Dopant activation in the source and drain locations is recovered during conversion from amorphous to crystalline structure. Presence of high carbon concentrations reduces dopant diffusion from the source and drain locations into the channel region. The techniques may be employed with respect to both planar and non-planar (e.g., FinFET and nanowire) transistors.
Legal claims defining the scope of protection, as filed with the USPTO.
1. An integrated circuit comprising: a source region and a drain region, each comprising an alloy of silicon, germanium, and at least 5 atomic percent carbon; and a semiconductor region distinct from and between the source region and the drain region.
2. The integrated circuit of claim 1 , wherein the alloy is Si x Ge 1-x-y C y .
3. The integrated circuit of claim 1 , wherein a carbon content of the alloy is at least 10 atomic percent.
4. The integrated circuit of claim 1 , wherein the alloy includes a dopant.
5. The integrated circuit of claim 4 , wherein the dopant is at least one of phosphorous, arsenic and antimony.
6. The integrated circuit of claim 1 , wherein the semiconductor region comprises at least one of silicon, silicon germanium, and germanium.
7. The integrated circuit of claim 1 , wherein the alloy is crystalline and applies a tensile strain to the semiconductor region of the integrated circuit.
8. The integrated circuit of claim 7 , wherein the crystalline alloy includes carbon-rich precipitates.
9. The integrated circuit of claim 1 , wherein the source region, drain region, and semiconductor region are configured in a non-planar transistor.
10. The integrated circuit of claim 1 , wherein the source region, drain region, and semiconductor region are configured in a planar transistor.
11. An integrated circuit comprising: a semiconductor body, the semiconductor body comprising one of a fin, nanowire, or nanoribbon; a gate structure at least above and adjacent sides of at least a portion of the semiconductor body, the gate structure including a gate electrode and a gate dielectric between the gate electrode and the at least a portion of the semiconductor body; and a source region and a drain region, the at least a portion of the semiconductor body being between the source region and the drain region, each of the source region and the drain region comprising an alloy of silicon, germanium, and carbon, wherein the carbon concentration is at least 5 atomic percent.
12. The integrated circuit of claim 11 , wherein the alloy is Si x Ge 1-x-y C y .
13. The integrated circuit of claim 11 , wherein a carbon content of the alloy is at least is at least 10 atomic percent.
14. The integrated circuit of claim 11 , wherein the alloy is crystalline and applies a tensile strain to a channel region of the integrated circuit.
15. The integrated circuit of claim 11 , wherein the alloy includes carbon-rich precipitates.
16. A method of forming an integrated circuit, the method comprising: forming a semiconductor body, the semiconductor body comprising one of a fin, nanowire, or nanoribbon; forming a gate structure at least above and adjacent sides of at least a portion of the semiconductor body, the gate structure including a gate electrode and a gate dielectric between the gate electrode and the at least a portion of the semiconductor body; forming a source trench to one side of the gate structure, the source trench corresponding to a source region; forming a drain trench to another side of the gate structure, the drain trench corresponding a drain region; depositing in both of the source trench and the drain trench an amorphous alloy of silicon, germanium, and carbon, wherein the carbon concentration is at least 5 atomic percent; and crystallizing the amorphous alloy of silicon, germanium, and carbon, the crystallizing applying a tensile strain to the at least a portion of the semiconductor body.
17. The method of claim 16 , wherein the amorphous alloy is Si x Ge 1-x-y C y .
18. The method of claim 16 , wherein a carbon content of the amorphous alloy is at least 10 atomic percent.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
December 24, 2015
February 11, 2020
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