Managed integrated circuit power supply distribution

1. A method for designing and fabricating an integrated circuit (IC) having a managed power distribution structure, the method comprising: creating, with a timing estimation program in conjunction with a model of a preliminary power distribution structure, a set of preliminary timing estimates for circuits on the IC; dividing, with an electronic design automation (EDA) program in conjunction with the set of preliminary timing estimates, the IC into a plurality of regions, each region of the plurality of regions including a corresponding virtual power island (VPI) electrically interconnected to supply power to circuits within the each region; identifying, with the timing estimation program, a worst-case timing path for circuits within each respective region of the plurality of regions; calculating, with a circuit simulation program, an alternating current (AC) draw and a direct current (DC) draw for circuits within each region of the plurality of regions; calculating with the EDA program, a worst-case AC transient current draw for circuits within each region of the plurality of regions; calculating, with the EDA program, resistances of a plurality of sets of vertical interconnects (VIs), each set of VIs of the plurality of sets of VIs electrically interconnected to a global power distribution structure and to a corresponding VPI within each region of the plurality of regions, the resistances of the plurality of sets of VIs calculated to manage a timing of the circuits within each region of the plurality of regions; and modifying, with an IC layout program, in accordance with the calculated resistances of the plurality of sets of VIs, the preliminary power distribution structure to create a managed power distribution structure that, during operation of the IC, provides a managed timing of the circuits within each region of the plurality of regions.

2. The method of claim 1 , wherein the model of the preliminary power distribution structure includes at least one VI and at least one horizontal interconnect (HI) electrically connected to a first VPI and electrically connected to a second VPI adjacent to the first VPI.

3. The method of claim 1 , further comprising creating, from a set of performance measurements of the IC, a set of preliminary timing estimates for circuits on the IC.

4. The method of claim 1 , wherein the dividing the IC into a plurality of regions includes creating a first region of the plurality of regions having a first set of preliminary timing estimates in a first range and creating a second region of the plurality of regions having a second set of preliminary timing estimates in a second range that is different than the first range.

5. The method of claim 1 , wherein the calculating resistances of a plurality of sets of VIs is performed based upon a worst-case timing path, a DC current draw, an AC current draw and a worst-case AC transient current draw for circuits within each region of the plurality of regions.

6. The method of claim 1 , wherein the modifying the preliminary power distribution structure includes modifying IC design data that is contained in at least one computer-readable design file.

7. The method of claim 1 , wherein the modifying the preliminary power distribution structure includes modifying dimensions of at least one horizontal interconnect (HI) electrically connected to a first VPI and electrically connected to a second VPI adjacent to the first VPI.

8. The method of claim 1 , wherein the modifying the preliminary power distribution structure includes modifying a diameter of at least one VI electrically interconnected to a global power distribution structure and to a VPI.

9. The method of claim 1 , wherein the modifying the preliminary power distribution structure includes changing a quantity of VIs that are electrically interconnected to a global power distribution structure and to a VPI.

10. The method of claim 1 , wherein the modifying the preliminary power distribution structure includes changing a quantity of horizontal interconnects (HIs) electrically connected to a first VPI and electrically connected to a second VPI adjacent to the first VPI.

11. The method of claim 1 , wherein the calculating resistances of a plurality of sets of VIs includes calculating resistances that provide, during the operation of the IC, a set of voltages to a corresponding set of VPIs, that maintain a timing performance of circuits in each region of the plurality of regions within a specified performance range.

12. The method of claim 11 wherein the specified performance range is based upon the timing performance of a nominal set of circuits within a region of the plurality of regions.