A path computation element (PCE) central controller (PCECC) comprising a memory comprising executable instructions and a processor coupled to the memory and configured to execute the instructions. Executing the instructions causes the processor to receive a request to compute a path through a network, the request comprising a plurality of computational tasks, divide the computational tasks into a plurality of groups of computational tasks, transmit at least some of the plurality of groups of computational tasks to a plurality of path computation clients (PCCs) for computation by the PCCs, and receive, from the PCCs, computation results corresponding to the plurality of groups of computational tasks.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A path computation element (PCE) central controller (PCECC) comprising: a memory comprising executable instructions; and a processor coupled to the memory and configured to execute the instructions, wherein executing the instructions causes the processor to: receive a request to compute a path through a network, the request comprising a plurality of path computational tasks for computing the path through the network; divide the plurality of path computational tasks for computing the path through the network into a plurality of groups of path computational tasks; transmit at least some of the plurality of groups of path computational tasks for computing the path through the network to a plurality of path computation clients (PCCs) for computation by the PCCs; receive, from the PCCs, computation results corresponding to the plurality of groups of path computational tasks for computing the path through the network; and compute, by the PCECC, the path through the network using the computation results corresponding to the plurality of groups of path computational tasks received from the PCCs.
2. The PCECC of claim 1 , wherein the PCECC transmits the at least some of the plurality of groups of path computational tasks to first PCCs configured in a dual operation mode as a PCC and as a PCE.
3. The PCECC of claim 1 , wherein the processor further performs first path computational tasks corresponding to one of the plurality of groups of path computational tasks.
4. The PCECC of claim 1 , wherein the processor further: transmits forwarding information corresponding to the path to at least some of the PCCs.
5. The PCECC of claim 4 , wherein the processor further: receives forwarding entry information from at least some of the PCCs; and updates a database of routing information with the received forwarding entry information.
6. The PCECC of claim 1 , wherein the PCECC receives the request to compute the path through the network from one of the plurality of PCCs.
7. The PCECC of claim 1 , wherein the PCECC is configured in a dual operation mode as a PCE and as a PCC.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
March 30, 2017
March 3, 2020
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