Display device, gate driving circuit and gate driving unit

1. A gate driving unit, comprising: a signal maintenance circuit which is configured to, during a period that a first clock signal input end of the signal maintenance circuit receives a first clock signal at a high level, output a high level from an output end of the signal maintenance circuit in accordance with a trigger signal at a high level inputted into a trigger signal input end of the signal maintenance circuit; a first-level output circuit, wherein a trigger signal input end of the first-level output circuit is connected to the output end of the signal maintenance circuit, and the first-level output circuit is configured to, during a period that a second clock signal input end of first-level output circuit receives a second clock signal at a high level, output a first-level driving signal at a high level from an output end of the first-level output circuit in accordance with the high level from the output end of the signal maintenance circuit; and a second-level output circuit, wherein a trigger signal input end of the second-level output circuit is connected to the output end of the first-level output circuit, and the second-level output circuit is configured to, during a period that a third clock signal input end of the second-level output circuit receives a third clock signal at a high level, output a second-level driving signal at a high level from an output end of the second-level output circuit in accordance with the high level from the output end of the first-level output circuit, wherein the second clock signal at the high level arrives upon the first clock signal at the high level ending, and the third clock signal at the high level arrives upon the second clock signal at the high level ending; wherein each of the first-level output circuit and the second-level output circuit further comprises a respective resetting signal input end and is configured to, when the respective resetting signal input end receives a resetting signal, reset the respective output end to be at a low level; wherein the resetting signal input end of the first-level output circuit is connected directly to the signal maintenance circuit, and the output end of the first-level output circuit is being reset under the control of a first resetting signal; and wherein the resetting signal input end of the second-level output circuit receives a second resetting signal, and the second resetting signal is the first clock signal.

2. The gate driving unit according to claim 1 , wherein: the signal maintenance circuit further comprises a resetting signal input end and is configured to, when the resetting signal input end of the signal maintenance circuit receives a resetting signal, reset the respective output end to be at a low level.

3. The gate driving unit according to claim 2 , wherein: the resetting signal input end of the signal maintenance circuit receives the resetting signal, and the signal maintenance circuit is configured to reset the output end of the signal maintenance circuit in accordance with the resetting signal.

4. The gate driving unit according to claim 3 , wherein: the signal maintenance circuit comprises a high-level maintenance sub-circuit and a level pull-down sub-circuit; the high-level maintenance sub-circuit is configured to, during the period that the first clock signal is at the high level, output the high level from the output end of the signal maintenance circuit in accordance with the inputted trigger signal at the high level; the level pull-down sub-circuit is configured to, during the period that the first clock signal is at the high level, enable the high-level maintenance sub-circuit to be electrically disconnected from a low reference voltage end, and upon the resetting signal at the high level arriving, enable the high-level maintenance sub-circuit to be electrically connected to the low reference voltage end, to reset the output end of the signal maintenance circuit to be at a low level; and the resetting signal arrives upon the second clock signal at the high level ends.

5. The gate driving unit according to claim 4 , wherein: the high-level maintenance sub-circuit comprises a first transistor, a second transistor and a third transistor; a drain electrode of the first transistor is connected to a trigger signal input end of the gate driving unit, a gate electrode of the first transistor and a gate electrode of the second transistor are connected to the first clock signal input end, a source electrode of the first transistor is connected to a drain electrode of the second transistor and a drain electrode of the third transistor, a source electrode of the third transistor is connected to the second clock signal input end, and a first node connecting a gate electrode of the third transistor and a source electrode of the second transistor serves as the output end of the signal maintenance circuit; and the level pull-down sub-circuit is further configured to, during the period that the first clock signal is at the high level, enable the first node to be electrically disconnected from the low reference voltage end, and upon the second clock signal at the high level ending, enable the first node to be electrically connected to the low reference voltage end, to pull down a level at the first node.

6. The gate driving unit according to claim 5 , wherein: the level pull-down sub-circuit comprises a tenth transistor, an eleventh transistor, a twelfth transistor, and a thirteenth transistor; and a gate electrode of the tenth transistor, a gate electrode of the eleventh transistor, a source electrode of the twelfth transistor and a drain electrode of the thirteenth transistor are connected to a second node, a drain electrode of the tenth transistor and a gate electrode of the thirteenth transistor are connected to the first node, a source electrode of the tenth transistor and a drain electrode of the eleventh transistor are connected to the drain electrode of the third transistor, a source electrode of the eleventh transistor is connected to the low reference voltage end, a drain electrode of the twelfth transistor is connected to a high reference voltage end, and a gate electrode of the twelfth transistor is connected to the resetting signal input end of the signal maintenance circuit.

7. The gate driving unit according to claim 6 , wherein: the first-level output circuit comprises a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, a first capacitor and a second capacitor; and a gate electrode of the fourth transistor is connected to the trigger signal input end of the first-level output circuit and the first node, a drain electrode of the fourth transistor is connected to the second clock signal input end, a source electrode of the fourth transistor is connected to a drain electrode of the fifth transistor and a gate electrode of the sixth transistor, a node connecting a gate electrode of the fifth transistor and a gate electrode of the seventh transistor is connected to the second node and serves as the resetting signal input end of the first-level output circuit, a source electrode of the fifth transistor and a source electrode of the seventh transistor are connected to the low reference voltage end, a drain electrode of the sixth transistor is connected to a circuit operating voltage end, the first capacitor is connected to the gate electrode and the source electrode of the fourth transistor, the second capacitor is connected to the gate electrode and a source electrode of the sixth transistor, and a third node connecting a drain electrode of the seventh transistor and the source electrode of the sixth transistor serves as the output end of the first-level output circuit.

8. The gate driving unit according to claim 7 , wherein: the second-level output circuit comprises an eighth transistor, a ninth transistor, a fourteenth transistor, a fifteenth transistor, a sixteenth transistor and a third capacitor; and a gate electrode of the fourteenth transistor is connected to a gate electrode of the sixth transistor, a drain electrode of the fourteenth transistor is connected to the trigger signal input end of the second-level output circuit and the third node, a source electrode of the fourteenth transistor is connected to a drain electrode of the fifteenth transistor and a drain electrode of the sixteenth transistor, a source electrode of the fifteenth transistor is connected to a gate electrode of the eighth transistor, a drain electrode of the eighth transistor is connected to the circuit operating voltage end, a source electrode of the ninth transistor and a source electrode of the sixteenth transistor are connected to the low reference voltage end, a node connecting a gate electrode of the ninth transistor and a gate electrode of the sixteenth transistor is connected to the first clock signal input end and serves as the resetting signal input end of the second-level output circuit, a gate electrode of the fifteenth transistor is connected to the third clock signal input end, the third capacitor is connected to the gate electrode and a source electrode of the eighth transistor, and a fourth node connecting the source electrode of the eighth transistor and a drain electrode of the ninth transistor serves as the output end of the second-level output circuit.

9. The gate driving unit according to claim 1 , wherein the first, second and third clock signals have a substantially identical clock cycle, and a duty ratio of approximately 1:2.

10. The gate driving unit according to claim 3 , wherein: the resetting signal is maintained at a low level within a first high-level period of the first clock signal and within a first high-level period of the second clock signal after the trigger signal at the high level has been received, and then jumped between a high level and a low level on approximately two-thirds of one clock cycle.

11. A gate driving circuit, comprising at least two gate driving units each according to claim 1 connected in a cascaded manner, wherein the second-level driving signal outputted from a current-level gate driving unit serves as the trigger signal inputted to the signal maintenance circuit of a next-level gate driving unit.

12. The gate driving circuit according to claim 11 , wherein, for each of the at least two gate driving units: the signal maintenance circuit, further comprises a resetting signal input end and is configured to, when the resetting signal input end of the signal maintenance circuit receives a resetting signal, reset the respective output end to be at a low level.

13. The gate driving circuit according to claim 12 , wherein, for each of the at least two gate driving units: the resetting signal input end of the signal maintenance circuit receives the resetting signal, and the signal maintenance circuit is configured to reset the output end of the signal maintenance circuit in accordance with the resetting signal.

14. The gate driving circuit according to claim 13 , wherein, for each of the at least two gate driving units: the signal maintenance circuit comprises a high-level maintenance sub-circuit and a level pull-down sub-circuit; the high-level maintenance sub-circuit is configured to, during the period that the first clock signal is at the high level, output the high level from the output end of the signal maintenance circuit in accordance with the inputted trigger signal at the high level; the level pull-down sub-circuit is configured to, during the period that the first clock signal is at the high level, enable the high-level maintenance sub-circuit to be electrically disconnected from a low reference voltage end, and upon the resetting signal at the high level arriving, enable the high-level maintenance sub-circuit to be electrically connected to the low reference voltage end, to reset the output end of the signal maintenance circuit to be at a low level; and the resetting signal arrives upon the second clock signal at the high level ending.

15. The gate driving circuit according to claim 14 , wherein, for each of the at least two gate driving units: the high-level maintenance sub-circuit comprises a first transistor, a second transistor and a third transistor; a drain electrode of the first transistor is connected to a trigger signal input end of the gate driving unit, a gate electrode of the first transistor and a gate electrode of the second transistor are connected to the first clock signal input end, a source electrode of the first transistor is connected to a drain electrode of the second transistor and a drain electrode of the third transistor, a source electrode of the third transistor is connected to the second clock signal input end, and a first node connecting a gate electrode of the third transistor and a source electrode of the second transistor serves as the output end of the signal maintenance circuit; and the level pull-down sub-circuit is further configured to, during the period that the first clock signal is at the high level, enable the first node to be electrically disconnected from the low reference voltage end, and upon the second clock signal at the high level ending, enable the first node to be electrically connected to the low reference voltage end, to pull down a level at the first node.

16. The gate driving circuit according to claim 15 , wherein, for each of the at least two gate driving units: the level pull-down sub-circuit comprises a tenth transistor, an eleventh transistor, a twelfth transistor, and a thirteenth transistor; and a gate electrode of the tenth transistor, a gate electrode of the eleventh transistor, a source electrode of the twelfth transistor and a drain electrode of the thirteenth transistor are connected to a second node, a drain electrode of the tenth transistor and a gate electrode of the thirteenth transistor are connected to the first node, a source electrode of the tenth transistor and a drain electrode of the eleventh transistor are connected to the drain electrode of the third transistor, a source electrode of the eleventh transistor is connected to the low reference voltage end, a drain electrode of the twelfth transistor is connected to a high reference voltage end, and a gate electrode of the twelfth transistor is connected to the resetting signal input end of the signal maintenance circuit.

17. The gate driving circuit according to claim 16 , wherein, for each of the at least two gate driving units: the first-level output circuit comprises a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, a first capacitor and a second capacitor; and a gate electrode of the fourth transistor is connected to the trigger signal input end of the first-level output circuit and the first node, a drain electrode of the fourth transistor is connected to the second clock signal input end, a source electrode of the fourth transistor is connected to a drain electrode of the fifth transistor and a gate electrode of the sixth transistor, a node connecting a gate electrode of the fifth transistor and a gate electrode of the seventh transistor is connected to the second node and serves as the resetting signal input end of the first-level output circuit, a source electrode of the fifth transistor and a source electrode of the seventh transistor are connected to the low reference voltage end, a drain electrode of the sixth transistor is connected to a circuit operating voltage end, the first capacitor is connected to the gate electrode and the source electrode of the fourth transistor, the second capacitor is connected to the gate electrode and a source electrode of the sixth transistor, and a third node connecting a drain electrode of the seventh transistor and the source electrode of the sixth transistor serves as the output end of the first-level output circuit.

18. The gate driving circuit according to claim 17 , wherein, for each of the at least two gate driving units: the second-level output circuit comprises an eighth transistor, a ninth transistor, a fourteenth transistor, a fifteenth transistor, a sixteenth transistor and a third capacitor; and a gate electrode of the fourteenth transistor is connected to a gate electrode of the sixth transistor, a drain electrode of the fourteenth transistor is connected to the trigger signal input end of the second-level output circuit and the third node, a source electrode of the fourteenth transistor is connected to a drain electrode of the fifteenth transistor and a drain electrode of the sixteenth transistor, a source electrode of the fifteenth transistor is connected to a gate electrode of the eighth transistor, a drain electrode of the eighth transistor is connected to the circuit operating voltage end, a source electrode of the ninth transistor and a source electrode of the sixteenth transistor are connected to the low reference voltage end, a node connecting a gate electrode of the ninth transistor and a gate electrode of the sixteenth transistor is connected to the first clock signal input end and serves as the resetting signal input end of the second-level output circuit, a gate electrode of the fifteenth transistor is connected to the third clock signal input end, the third capacitor is connected to the gate electrode and a source electrode of the eighth transistor, and a fourth node connecting the source electrode of the eighth transistor and a drain electrode of the ninth transistor serves as the output end of the second-level output circuit.

19. The gate driving circuit according to claim 11 , wherein the first, second and third clock signals have a substantially identical clock cycle, and a duty ratio of approximately 1:2.

20. A display device, comprising the gate driving circuit according to claim 11 .