Interpolation amplifier and source driver including the same

1. A source driver comprising: an interpolation amplifier configured to generate an interpolation voltage based on a received plurality of input voltages and output the interpolation voltage to a display panel; and an input selector configured to receive a first voltage, a second voltage having a different voltage level from the first voltage, and at least lower bits of pixel data having bits, and selectively provide at least one of the first and second voltages as the plurality of input voltages in response to the lower bits of the pixel data, wherein the interpolation amplifier includes, a first differential input pair configured to receive a first input voltage from among the plurality of input voltages, a second differential input pair configured to receive a second input voltage from among the plurality of input voltages, a third differential input pair configured to receive a third input voltage from among the plurality of input voltages, and a fourth differential input pair configured to receive a fourth input voltage from among the plurality of input voltages, each of the first differential input pair and third differential input pair includes a first type transistor, and each of the second differential input pair and fourth differential input pair includes a second type transistor.

2. The source driver of claim 1 , wherein the first and second differential input pairs constitute a first input circuit from among a plurality of input circuits having a rail-to-rail structure, the third and fourth differential input pairs constitute a second input circuit from among the plurality of input circuits, and the first, second, third and fourth voltages are independent from one another.

3. The source driver of claim 1 , wherein, when a least significant bit of the pixel data is at a first logic level, the input selector provides one of the first and second voltages as the first input voltage and provides the other one of the first and second voltages as the second input voltage.

4. The source driver of claim 3 , wherein, when the least significant bit of the pixel data is at a second logic level, the input selector provides one of the first and second voltages as the first and second input voltages.

5. The source driver of claim 1 , wherein the input selector provides one of the first and second voltages as the third and fourth input voltages.

6. The source driver of claim 1 , wherein, when a least significant bit of the pixel data is at a first logic level, the input selector provides the second voltage as the first input voltage if values of some of the bits of the pixel data are less than an intermediate value of the some of the bits, and provides the first voltage as the first input voltage when values of the some of the bits are greater than the intermediate value.

7. The source driver of claim 6 , wherein the first type transistor is an n-channel metal-oxide-semiconductor (NMOS) transistor, and the second type transistor is a p-channel metal-oxide-semiconductor (PMOS) transistor, wherein a level of the second voltage is higher than a level of the first voltage.

8. The source driver of claim 1 , wherein the input selector provides the first voltage as the first input voltage and provides the second voltage as the second input voltage when a polarity signal is at a first logic level, and provides the first voltage as the first input voltage and provides the second voltage as the second input voltage when the polarity signal is at a second logic level.

9. The source driver of claim 8 , wherein a logic level of the polarity signal is switched per frame of the display panel or per line of the frame.

10. The source driver of claim 8 , further comprising: a first decoder configured to output the first and second voltages based on first gamma reference voltages within a first voltage range and a second decoder configured to output the first and second voltages based on second gamma reference voltages within a second voltage range different from the first voltage range, wherein the first decoder outputs the first and second voltages when the polarity signal is at the first logic level and the second decoder outputs the first and second voltages when the polarity signal is at the second logic level.

11. The source driver of claim 1 , wherein the interpolation amplifier further includes fifth to eighth differential input pairs configured to respectively receive fifth to eighth input voltages from among the plurality of input voltages.

12. A source driver comprising: a decoder configured to receive gamma voltages and pixel data, the pixel data having N bits, N being an integer equal to, or greater than, 4 and output two voltages from among the gamma voltages as first and second voltages in response to at least some of upper bits of the pixel data, voltage levels of the two voltages being adjacent to each other; an input selector, in response to some of the lower bits of the pixel data, configured to selectively redundantly distribute the first and second voltages and output distributed voltages; and an interpolation amplifier comprising a plurality of input circuits respectively comprising first and second conductive differential input pairs, the plurality of input circuits having a rail to rail structure, the first and second conductive differential input pairs in at least one of the plurality of input circuits respectively receive different voltages from among the distributed voltages output from the input selector.

13. The source driver of claim 12 , wherein the interpolation amplifier generates one of 2 K interpolation voltages, and comprises m input circuits, K being an integer of 2 or more, and less than N, m being (2 K )/2.

14. The source driver of claim 13 , wherein the input selector outputs the distributed voltages in response to lower K bits (K is an integer of 2 or more, and less than N) of the pixel data.

15. The source driver of claim 12 , wherein the first and second conductive differential input pairs in at least one other input circuit from among the plurality of input circuits receive one of the distributed voltages.

16. A source driver comprising: a digital to analog converter including a first decoder and a second decoder, the digital to analog converter configured to receive positive gamma voltages, negative gamma voltages, first pixel data and a polarity signal, the first decoder configured to select two negative gamma voltages based on the first pixel data, the second decoder configured to select two positive gamma voltages based on the first pixel data, the digital to analog converter is further configured to output two gamma voltages based on the polarity signal, the two gamma voltages being either the selected two negative gamma voltages or the selected two positive gamma voltages; an input selector configured to output a plurality of distributed voltages based on the two output gamma voltages, second pixel data and the polarity signal; and an interpolation amplifier including a plurality of input circuits, the interpolation amplifier configured to output an output voltage based on the plurality of distributed voltages.

17. The source driver of claim 16 wherein the polarity signal may change per line or per frame of a display panel.

18. The source driver of claim 16 wherein the digital to analog converter is configured to receive 2 (N-K) positive gamma voltages and 2 (N-K) negative gamma voltages, N being the number of bits in the first pixel data, and K being the number of bits in the second pixel data.

19. The source driver of claim 16 , wherein a number of the plurality of distributed voltages is between 3 and 2 K , K being the number of bits in the second pixel data.

20. The source driver of claim 19 wherein each of the input circuits includes two differential input pairs, and at least one of the input circuits receive two distributed voltages among the plurality of distributed voltages.