An RC-IGBT includes a first electrode disposed on a first main surface of a semiconductor substrate over a transistor region and a diode region. The semiconductor substrate includes a MOS gate structure on a first main surface side in the transistor region. The RC-IGBT includes: an interlayer dielectric covering a gate electrode of the MOS gate structure, and having a contact hole exposing a semiconductor layer; and a barrier metal disposed in the contact hole. The first electrode enters the contact hole, is in contact with the semiconductor layer of the MOS gate structure through the barrier metal, and is in direct contact with a semiconductor layer in the diode region of the semiconductor substrate.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A semiconductor device comprising: a semiconductor substrate having a first main surface and a second main surface, and including a transistor region forming a transistor extending from said first main surface to said second main surface and a diode region forming a diode extending from said first main surface to said second main surface; and a first electrode disposed on said first main surface of said semiconductor substrate over said transistor region and said diode region, wherein said semiconductor substrate includes a MOS gate structure on a first main surface side in said transistor region, said semiconductor device includes: an interlayer dielectric covering a gate electrode of said MOS gate structure, and having a contact hole exposing a semiconductor layer of said MOS gate structure; and a barrier metal disposed in said contact hole, said first electrode enters said contact hole, is in contact with the semiconductor layer of said MOS gate structure through said barrier metal in said contact hole, and is in direct contact with a semiconductor layer in said diode region of said semiconductor substrate, said barrier metal includes titanium nitride, titanium carbide, or titanium silicide, and no barrier metal is disposed on said first main surface of said semiconductor substrate in said diode region.
2. The semiconductor device according to claim 1 , wherein said semiconductor substrate includes a collector layer of a second conductivity type on a second main surface side in said transistor region, and said transistor region forms an IGBT.
3. The semiconductor device according to claim 1 , wherein said first electrode is an aluminum alloy.
4. The semiconductor device according to claim 1 , wherein said barrier metal includes silicide at a contact interface with the semiconductor layer of said MOS gate structure.
5. The semiconductor device according to claim 1 , wherein said contact hole includes a first width at a lower surface of said interlayer dielectric and a second width at an upper surface of said interlayer dielectric, said second width being larger than said first width, and a width of said contact hole changes at a constant rate from said first width to said second width.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
December 11, 2017
March 24, 2020
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