Once a delay locked loop has been locked to a clock signal, an omitted clock cycle is injected into the input of the delay locked loop without stopping the operation of the delay locked loop. The omitted cycle is later detected at an output of the delay locked loop, and the delay between the input and output is determined based on the time the omitted cycle requires to propagate through the delay locked loop. Once determined, the number of cycles of delay for the delay locked loop can be used in conjunction with an internal clock signal to launch data and/or data strobes from memory devices and memory controllers such that the proper phase alignment and clock cycle alignment is achieved.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method for operating a delay locked loop having a first end and a second end, comprising: providing a clock signal to the first end of the delay locked loop, wherein the clock signal is a periodic signal that includes a plurality of cycles; detecting that the delay locked loop has locked to the clock signal; after detecting that the delay locked loop has locked, manipulating a cycle of the plurality of cycles of the clock signal as the clock signal is provided to the delay locked loop at the first end; detecting the manipulated cycle of the plurality of cycles at a location within the delay locked loop; and determining a number of cycles of the clock signal in a delay of at least a portion the delay locked loop, wherein the number of clock cycles in the delay corresponds to a number of clock cycles that transpired while the manipulated cycle of the plurality of cycles propagates from the first end of the delay locked loop to the location within the delay locked loop.
2. The method of claim 1 , wherein determining the number of cycles of the clock signal in the delay further comprises: starting a counter when the manipulated cycle of the plurality of cycles is provided to the first end of the delay locked loop; and determining the number of cycles of the clock signal in the delay based on the counter when the manipulated cycle is detected at the location within the delay locked loop.
3. The method of claim 1 , wherein the location within the delay locked loop is a location other than the second end of the delay locked loop.
4. The method of claim 1 , wherein manipulating the cycle of the plurality of cycles further comprises reducing an amplitude of the cycle being manipulated.
5. The method of claim 1 wherein detecting the manipulated cycle of the plurality of cycles further comprises comparing a signal at the location within the delay locked loop during a current cycle with the signal at the location within the delay locked loop during a previous cycle.
6. The method of claim 1 , further comprising: after determining the number of cycles of the clock signal in the delay, outputting a signal indicating that the number of cycles has been determined; and while outputting the signal indicating that the number of cycles has been determined, outputting at least one additional signal representative of the number of cycles in the delay.
7. The method of claim 1 , wherein manipulating the cycle further comprises at least one of: gating off the clock signal from the first end of the delay locked loop for a time corresponding to the cycle being manipulated; or holding an input at the first end of the delay locked loop low during a cycle of the clock signal corresponding to the cycle being manipulated.
8. A method of operation of a memory that includes a delay locked loop having a first end and a second end, the method comprising: providing a clock signal to the first end of the delay locked loop, wherein the clock signal is a periodic signal that includes a plurality of cycles; detecting that the delay locked loop has locked to the clock signal, wherein the delay locked loop generates an internal clock signal to provide phase alignment for data output from the memory; after detecting that the delay locked loop has locked to the clock signal, manipulating a cycle of the plurality of cycles of the clock signal as the clock signal is provided to the delay locked loop at the first end; detecting, at a location within the delay locked loop, the manipulated cycle of the plurality of cycles; determining a number of cycles of the clock signal in a delay of a portion of the delay locked loop, wherein the number of clock cycles in the delay corresponds to a number of clock cycles that transpired while the manipulated cycle of the plurality of cycles propagates from the first end of the delay locked loop to the location within the delay locked loop; and initiating a launch of data from the memory based on the internal clock signal and a latency value stored in a register on the memory.
9. The method of operation of the memory of claim 8 , wherein initiating the launch of data further comprises initiating the launch of data such that data output from the memory corresponds to a selected clock cycle of an external clock signal.
10. The method of operation of the memory of claim 9 , wherein the selected clock cycle is determined based on the latency value stored in the register on the memory.
11. The method of operation of the memory of claim 10 , wherein the latency value stored in the register on the memory is representative of a number of clock cycles of the external clock signal to transpire between receipt of a read operation code by the memory and the output of data corresponding to the read operation code by the memory.
12. The method of claim 10 , wherein the latency value stored in the register on the memory is representative of the number of clock cycles in the delay.
13. The method of claim 8 , wherein initiating the launch of data further comprises initiating the launch of data based on the internal clock signal such that data output from the memory is phase aligned with an external clock signal.
14. The method of claim 8 , wherein determining the number of cycles of the clock signal in the delay further comprises: starting a counter when the manipulated cycle of the plurality of cycles is provided to the first end of the delay locked loop; and determining the number of cycles of the clock signal in the delay based on the counter when the manipulated cycle is detected at the location within the delay locked loop.
15. The method of claim 8 , wherein manipulating the cycle of the plurality of cycles further comprises at least one of: reducing an amplitude of the cycle being manipulated; gating off the clock signal from the first end of the delay locked loop for a time corresponding to the cycle being manipulated; or holding an input at the first end of the delay locked loop low during a cycle of the clock signal corresponding to the cycle being manipulated.
16. An apparatus, comprising: a delay locked loop configured to receive an input at a first end and generate a feedback clock signal at a second end based on the input, wherein the delay locked loop has a delay between the first end and a location within the delay locked loop; an input block coupled to the delay locked loop, wherein the input block is configured to receive a clock signal having a plurality of cycles and output an input clock signal to the input of the delay locked loop, wherein the input block is configured to selectively manipulate at least one cycle of the input clock signal in response to a skip-control signal; and a loop monitor coupled to the delay locked loop and the input block, wherein the loop monitor is configured to, in response to receiving an indication that the delay locked loop has locked to the clock signal: assert the skip-control signal; cause a counter to start counting a number of cycles of the clock signal when the skip-control signal is asserted; and cause the counter to stop counting the number of cycles of the clock signal when the at least one manipulated clock cycle of the input clock signal is detected at the location within the delay locked loop.
17. The apparatus of claim 16 , wherein loop monitor is configured to: determine a number of cycles in the delay of the delay locked loop based on the counted number of cycles of the clock signal; and output a signal indicating detection is complete and at least one signal representative of the number of cycles in the delay.
18. The apparatus of claim 17 , further comprising: control circuitry coupled to the loop monitor, wherein the control circuitry is configured to initiate an output signal from the apparatus based on an internal clock signal generated by the delay locked loop and the signal representative of the number of cycles in the delay.
19. The apparatus of claim 18 , wherein the apparatus is a memory that is configured to receive an external clock signal, wherein the control circuitry is configured to initiate the output signal such that the output signal is output from the memory in phase alignment with the external clock signal during a selected cycle of the external clock signal.
20. The apparatus of claim 19 , wherein the memory is a magnetic random access memory (MRAM).
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February 15, 2019
March 31, 2020
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