According to various embodiments, a memory cell may include: a field-effect transistor structure comprising a channel region and a gate structure disposed at the channel region, the gate structure comprising a gate electrode structure and a gate isolation structure disposed between the gate electrode structure and the channel region; and a memory structure comprising a first electrode structure, a second electrode structure, and at least one remanent-polarizable layer disposed between the first electrode structure and the second electrode structure; wherein the first electrode structure of the memory structure is electrically conductively connected to the gate electrode structure of the field-effect transistor structure.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A memory cell, comprising: a field-effect transistor structure comprising a channel region and a gate structure disposed on at least two opposing sides of the channel region, the gate structure comprising a gate electrode structure and a gate isolation structure disposed between the gate electrode structure and the channel region; and a memory structure comprising a first electrode structure, a second electrode structure, and at least one remanent-polarizable layer disposed between the first electrode structure and the second electrode structure, wherein the first electrode structure of the memory structure is electrically conductively connected to the gate electrode structure of the field-effect transistor structure.
2. The memory cell of claim 1 , wherein the channel region is a fin-shaped channel region, and wherein the gate structure is disposed on at least two opposing planar surfaces of the fin-shaped channel region.
3. The memory cell of claim 1 , wherein the channel region comprises a nanosheet or nanowire, and wherein the gate isolation structure completely surrounds a perimeter of the nanosheet or nanowire.
4. The memory cell of claim 1 , wherein at least part of the gate isolation structure has a curved shape.
5. The memory cell of claim 1 , wherein the field-effect transistor structure further comprises a semiconductor portion and at least a first source/drain region and a second source/drain region disposed in the semiconductor portion; and wherein the channel region extends in the semiconductor portion from the first source/drain region to the second source/drain region.
6. The memory cell of claim 1 , wherein the first electrode structure of the memory structure is in direct physical contact with the gate electrode structure of the field-effect transistor structure.
7. The memory cell of claim 6 , further comprising: a contact metallization disposed over the field-effect transistor structure and the memory structure, the contact metallization comprising at least one memory contact structure electrically contacting the second electrode structure of the memory structure.
8. The memory cell of claim 1 , further comprising: one or more metallization structures disposed over the field-effect transistor structure, the one or more metallization structures configured to electrically connect the gate electrode structure of the field-effect transistor structure to the first electrode structure of the memory structure.
9. The memory cell of claim 8 , wherein the one or more metallization structures comprise a contact metallization at least partially disposed between the field-effect transistor structure and the memory structure.
10. The memory cell of claim 8 , wherein the one or more metallization structures comprise a contact metallization and a single- or multilevel metallization disposed over the contact metallization; wherein both the contact metallization and at least one level of the single- or multilevel metallization are disposed between the field-effect transistor structure and the memory structure.
11. The memory cell of claim 1 , wherein the at least one remanent-polarizable layer comprises at least one ferroelectric material.
12. The memory cell of claim 1 , wherein the first electrode structure comprises at least one layer of an electrically conductive material, and wherein a lateral dimension of the at least one layer is greater than a lateral dimension of the at least one remanent-polarizable layer or greater than the lateral dimension of the second electrode structure.
13. The memory cell of claim 8 , wherein the memory structure has a concave shape.
14. The memory cell of claim 1 , wherein the memory structure has one or more angled sections and/or one or more arcuated sections.
15. The memory cell of claim 1 , wherein the field-effect transistor structure is a fin field-effect transistor structure.
16. The memory cell of claim 1 , wherein the field-effect transistor structure is a nanosheet field-effect transistor structure.
17. The memory cell of claim 1 , wherein the field-effect transistor structure is a nanowire field-effect transistor structure.
18. The memory cell of claim 1 , wherein the gate electrode structure, the gate isolation structure, and the channel region forming a first capacitor structure defining a capacitor area of a first area size; and wherein the first electrode structure, the at least one remanent-polarizable layer, and the second electrode structure forming a second capacitor structure defining a capacitor area of a second area size less than the first area size.
19. A memory cell, comprising: a field-effect transistor structure comprising a channel region and a gate structure disposed on at least two opposing sides of the channel region, the gate structure comprising a gate electrode structure and a gate isolation structure disposed between the gate electrode structure and the channel region, the gate electrode structure and the gate isolation structure forming a first capacitor structure with a first capacitor area of a first area size; a memory structure comprising a first electrode structure, a second electrode structure, and at least one remanent-polarizable layer disposed between the first electrode structure and the second electrode structure, the second electrode structure and the at least one remanent-polarizable layer forming a second capacitor structure with a second capacitor area of a second area size less than the first area size.
20. A method for processing a memory cell, the method comprising: forming a field-effect transistor structure, the field-effect transistor structure comprising a channel region and a gate structure disposed on at least two opposing sides of the channel region, the gate structure comprising a gate electrode structure and a gate isolation structure disposed between the gate electrode structure and the channel region; forming one or more metallization structures over the field-effect transistor structure; and forming a memory structure over the one or more metallization structures, the memory structure comprising a first electrode structure, a second electrode structure, and at least one remanent-polarizable layer disposed between the first electrode structure and the second electrode structure; wherein the first electrode structure of the memory structure is electrically conductively connected to the gate electrode structure of the field-effect transistor structure via the one or more metallization structures.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
September 27, 2019
April 14, 2020
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