The present invention provides fin cut techniques in a replacement gate process for finFET fabrication. In one aspect, a method of forming a finFET employs a dummy gate material to pin a lattice constant of patterned fins prior to a fin cut thereby preventing strain relaxation. A dielectric fill in a region of the fin cut (below the dummy gates) reduces an aspect ratio of dummy gates formed from the dummy gate material in the fin cut region, thereby preventing collapse of the dummy gates. FinFETs formed using the present process are also provided.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method of forming a fin field-effect transistor (finFET), the method comprising: patterning at least one fin in a substrate; forming an oxide layer on the at least one fin; depositing a first dummy gate material onto the oxide layer over the at least one fin, wherein the first dummy gate material serves to pin a lattice constant of the at least one fin; depositing a hardmask on the first dummy gate material; forming a trench in the first dummy gate material and the oxide layer over at least one region of the at least one fin using the hardmask; extending the trench into the substrate, removing the at least one region of the at least one fin cutting the at least fin into multiple segments, wherein the trench has vertical sidewalls extending from the hardmask down into the substrate whereby the trench contacts the first dummy gate material which comprises amorphous silicon; after the at least one region of the at least one fin has been removed and the trench has been extended into the substrate, partially filling the trench with a first dielectric to a level above the at least one fin; depositing a second dummy gate material into the trench on top of the first dielectric such that the first dummy gate material and the second dummy gate material are present over the at least one fin; concurrently patterning the first dummy gate material and the second dummy gate material into individual dummy gates, wherein the first dummy gate material and the second dummy gate material are concurrently patterned after the cutting of the at least one fin, wherein at least one of the dummy gates is disposed on the first dielectric and at least another one of the dummy gates is disposed on the at least one fin, and wherein the at least one dummy gate disposed on the first dielectric has an aspect ratio less than an aspect ratio of the at least one dummy gate disposed on the at least one fin; forming source and drain regions on opposite sides of the dummy gates, wherein the source and drain regions are formed after the cutting of the at least one fin; surrounding the dummy gates with a second dielectric; selectively removing the dummy gates forming gate trenches in the second dielectric; and forming replacement gates in the gate trenches.
2. The method of claim 1 , wherein the substrate comprises a semiconductor wafer.
3. The method of claim 1 , wherein second dummy gate material comprises amorphous silicon.
4. The method of claim 1 , further comprising: forming the hardmask on the first dummy gate material patterned with a footprint and location of the trench over the at least one region of the at least one fin; and patterning the first dummy gate material through the hardmask with a first etch stopping on the oxide layer; and patterning the oxide layer using a second etch to form the trench in the first dummy gate material and the oxide layer.
5. The method of claim 1 , further comprising: filling the trench with the first dielectric; and recessing the first dielectric to the level above the at least one fin.
6. The method of claim 1 , wherein the first dielectric is selected from the group consisting of: silicon dioxide and silicon nitride.
7. The method of claim 1 , further comprising: recessing the second dummy gate material to a target dummy gate height.
8. The method of claim 1 , wherein the first dummy gate material and the second dummy gate material are patterned into the dummy gates using a sidewall image transfer (SIT) process.
9. The method of claim 1 , further comprising: forming gate spacers on opposite sides of the dummy gates such that the source and drain regions are offset from the dummy gates by the gate spacers.
10. A method of forming a finFET, the method comprising: patterning at least one fin in a substrate; forming an oxide layer on the at least one fin; depositing a dummy gate material onto the oxide layer over the at least one fin, wherein the dummy gate material serves to pin a lattice constant of the at least one fin; depositing a hardmask on the dummy gate material; forming a trench in the dummy gate material and the oxide layer over at least one region of the at least one fin using the hardmask; extending the trench into the substrate, removing the at least one region of the at least one fin cutting the at least fin into multiple segments, wherein the trench has vertical sidewalls extending from the hardmask down into the substrate whereby the trench contacts the dummy gate material which comprises amorphous silicon; after the at least one region of the at least one fin has been removed and the trench has been extended into the substrate, filling the trench with a first dielectric; patterning the dummy gate material into individual dummy gates, wherein the dummy gate material deposited before the cutting of the at least one fin is patterned after the cutting of the at least one fin, and wherein the first dielectric is at a same height as the dummy gates; surrounding the dummy gates with a second dielectric; selectively removing the dummy gates forming gate trenches in the second dielectric; and forming replacement gates in the gate trenches.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
January 25, 2017
April 14, 2020
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