Enhancement-mode GaN transistor with selective and nonselective etch layers for improved uniformity in GaN spacer thickness

1. A method of forming a transistor with a uniform spacer layer in areas surrounding the transistor gate, comprising: providing a transistor gate structure comprising: a barrier layer; a spacer layer disposed above the barrier layer, the spacer layer comprising a column III-V material; a first layer comprising p-type or compensated column III-V material disposed above the spacer layer; an etch stop layer comprising a p-type Al-containing column III-V material disposed above the spacer layer and the first layer comprising p-type or compensated column III-V material; and a second layer comprising p-type or compensated column III-V material positioned above the etch stop layer, the second layer comprising p-type or compensated column III-V material being thicker than the first layer comprising p-type or compensated column III-V material; positioning a mask over a gate region of the second layer comprising p-type or compensated column III-V material; performing a first etch of the second layer comprising p-type or compensated column III-V material outside the gate region with an etch recipe that is selective to the p-type Al-containing column III-V material of the etch stop layer, such that the etch stops on the etch stop layer; performing a second etch through the mask with an etch recipe that is non-selective to the p-type Al-containing column III-V material of the etch stop layer, such that the etch stop layer and the first layer comprising p-type or compensated column III-V material are completely etched outside the gate region covered by the mask, and the entire spacer layer outside the gate region covered by the mask is partially and uniformly etched.

2. The method of claim 1 , wherein the spacer layer comprises GaN.

3. The method of claim 1 , wherein the first and second layers of p-type or compensated column III-V material comprise pGaN.

4. The method of claim 1 , wherein the etch stop layer comprises pAlGaN or pAlInGaN.

5. The method of claim 4 , wherein the first and second layers of p-type or compensated column III-V material comprise pAlGaN or pAlInGaN, and the Al content of the first and second layers is less than Al content of the etch stop layer.

6. The method of claim 1 , wherein the spacer layer has a thickness of 1 nm-6 nm, the first layer comprising p-type or compensated column III-V material has a thickness of 1 nm-30 nm, the etch stop layer has a thickness of 0.5 nm 2 nm, and the second layer comprising p-type or compensated column III-V material has a thickness of 20 nm-100 nm.

7. The method of claim 1 , wherein the second etch results in the spacer layer being thicker in the gate region than outside the gate region, and the thickness of the spacer layer outside the gate region is substantially uniform.

8. The method of claim 1 , further comprising an additional etch stop layer disposed above the second layer comprising p-type or compensated column III-V material, and an additional layer of p-type or compensated column III-V material disposed above the additional etch stop layer, wherein the thickness of the structure between the barrier layer and the etch stop layer is less than the thickness of the structure between the etch stop layer and the additional etch stop layer, and wherein an additional etch is performed for the additional etch stop layer, resulting in graduated etching.

9. The method of claim 8 , wherein the additional etch stop layer has a different Al concentration and/or a different thickness than the etch stop layer.