A method for manufacturing a semiconductor device includes forming a first active region on a semiconductor substrate, forming a semiconductor layer on the first active region, patterning the semiconductor layer into a plurality of fins extending from the first active region vertically with respect to the semiconductor substrate, wherein the first active region is located at bottom ends of the plurality of fins, forming a silicide layer on exposed portions of the first active region, forming an electrically conductive contact on the silicide region, forming a second active region on top ends of each of the plurality of fins, and forming a gate structure between the plurality of fins, wherein the gate structure is positioned over the first active region and under the second active region.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A semiconductor device, comprising: a substrate; a source/drain region on the substrate; a plurality of fins extending from the source/drain region vertically with respect to the substrate, wherein the source/drain region is located under bottom ends of the plurality of fins; a silicide layer on exposed portions of the source/drain region; an electrically conductive contact on the silicide layer; wherein the silicide layer is on a top surface of the source/drain region and extends from the top surface toward the substrate to include a portion wrapped around an edge of the source/drain region; and a spacer layer, wherein the spacer layer comprises: a first spacer layer portion formed on the portion of the silicide layer wrapped around the edge of the source/drain region; and a second spacer layer portion formed on the silicide layer, wherein the second spacer layer portion covers a top surface of the silicide layer; a dielectric layer on the top surface of the second spacer layer portion; and a gate structure on the top surface of the second spacer layer portion and between the dielectric layer and a fin of the plurality of fins; wherein the second spacer layer portion is under the gate structure and between the top surface of the silicide layer and the gate structure; wherein the plurality of fins and the edge extend in opposite directions perpendicular to the top surface of the source/drain region; and wherein the semiconductor device comprises a vertical field-effect transistor (FET) device configured to carry current through the plurality of fins in a direction perpendicular to a top surface of the substrate.
2. The semiconductor device according to claim 1 , wherein the first spacer layer portion is formed on an isolation region, and the isolation region is located under the first spacer layer portion.
3. The semiconductor device according to claim 1 , wherein the electrically conductive contact extends through an opening in the second spacer layer portion to contact the top surface of the silicide layer.
4. The semiconductor device according to claim 1 , further comprising a second spacer layer on the gate structure.
5. The semiconductor device according to claim 1 , further comprising: a plurality of source/drain regions on top ends of each of the plurality of fins; wherein the gate structure is recessed to a height lower than a height of the plurality of fins and is positioned under a source/drain region of the plurality of source/drain regions.
6. The semiconductor device according to claim 5 , further comprising a second spacer layer on the gate structure between the source/drain region and the gate structure.
7. The semiconductor device according to claim 1 , wherein the dielectric layer on the top surface of the second spacer layer portion encapsulates the gate structure.
8. A semiconductor device, comprising: a substrate; a first active region on the substrate; a plurality of fins extending from the first active region vertically with respect to the substrate, wherein the first active region is located under bottom ends of the plurality of fins; a silicide layer on portions of the first active region; an electrically conductive contact on the silicide layer; wherein the silicide layer is on a top surface of the first active region and extends from the top surface toward the substrate to include a portion wrapped around an edge of the first active region; a second active region on top ends of each of the plurality of fins; a gate structure, wherein the gate structure is positioned over the first active region and under the second active region; and a spacer layer, wherein the spacer layer comprises: a first spacer layer portion formed on the portion of the silicide layer wrapped around the edge of the first active region; and a second spacer layer portion formed on the silicide layer, wherein the second spacer layer portion covers a top surface of the silicide layer; and a dielectric layer on the top surface of the second spacer layer portion; wherein the gate structure is on the top surface of the second spacer layer portion and between the dielectric layer and a fin of the plurality of fins; wherein the second spacer layer portion is under the gate structure and between the top surface of the silicide layer and the gate structure; wherein the plurality of fins and the edge extend in opposite directions perpendicular to the top surface of the first active region; and wherein the semiconductor device comprises a vertical field-effect transistor (FET) device configured to carry current through the plurality of fins in a direction perpendicular to a top surface of the substrate.
9. The semiconductor device according to claim 8 , wherein the first spacer layer portion is formed on an isolation region, and the isolation region is located under the first spacer layer portion.
10. The semiconductor device according to claim 8 , wherein the electrically conductive contact extends through an opening in the second spacer layer portion to contact the top surface of the silicide layer.
11. The semiconductor device according to claim 8 , further comprising a second spacer layer on the gate structure between the second active region and the gate structure.
12. The semiconductor device according to claim 8 , wherein the dielectric layer on the top surface of the second spacer layer portion encapsulates the gate structure.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
July 20, 2017
April 21, 2020
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