Various self-aligned interconnect structures are disclosed herein. An exemplary interconnect structure includes a first dielectric layer disposed over a substrate; a first conductive feature disposed in the first dielectric layer; an etch stop layer disposed over a top surface of the first dielectric layer and a top surface of the first conductive feature; a second dielectric layer disposed over the first dielectric layer; and a second conductive feature disposed in the second dielectric layer. The top surface of the first conductive feature is lower than the top surface of the first dielectric layer. The etch stop layer includes a portion that extends between the top surface of the first conductive feature and the top surface of the first dielectric layer, on which the second conductive feature may or may not be disposed. In some implementations, the second conductive feature may be a via feature.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method for forming a multi-layer interconnection (MLI) structure, the method comprising: forming a first etch stop layer over a substrate, wherein the first etch stop layer has a substantially planar top surface; forming a first dielectric layer over the substantially planar top surface of the first etch stop layer; forming a first metal line of the MLI structure in the first dielectric layer, wherein a top surface of the first metal line is lower than a top surface of the first dielectric layer, and further wherein the first metal line extends through the first etch stop layer and is connected to a conductive feature; forming a second etch stop layer over the top surface of the first dielectric layer and the top surface of the first metal line, such that the second etch stop layer has a non-planar top surface; forming a second dielectric layer disposed over the first dielectric layer and the second etch stop layer; and forming a second metal line of the MLI structure in the second dielectric layer, wherein the second metal line is connected to the first metal line.
2. The method of claim 1 , further comprising forming a via of the MLI structure in the second dielectric layer, wherein the via connects the second metal line to the first metal line.
3. The method of claim 2 , wherein: the second etch stop layer includes a portion that extends between the top surface of the first metal line and the top surface of the first dielectric layer; and the via is disposed on the portion of the second etch stop layer that extends between the top surface of the first metal line and the top surface of the first dielectric layer.
4. The method of claim 2 , wherein: the second etch stop layer includes a portion that extends between the top surface of the first metal line and the top surface of the first dielectric layer; and the via is not disposed on the portion of the second etch stop layer that extends between the top surface of the first metal line and the top surface of the first dielectric layer.
5. The method of claim 2 , wherein the via extends through the second etch stop layer disposed on the top surface of the first metal line and the via has a bottom surface that is lower than the top surface of the first dielectric layer.
6. The method of claim 2 , wherein the forming the second metal line of the MLI structure and the via in the second dielectric layer includes: performing a first lithography process to form a first patterned mask layer over the second dielectric layer, wherein the first patterned mask layer has a first opening; performing a second lithography process to form a second patterned mask layer over the first patterned mask layer, wherein the second patterned mask layer has a second opening that overlaps the first opening and the second patterned mask layer partially fills the first opening; etching the second dielectric layer using the second patterned mask layer to form a trench that extends partially through the second dielectric layer; after removing the second patterned mask layer, etching the second dielectric layer using the first patterned mask layer, such that the trench extends through the second dielectric layer and the second etch stop layer to expose the first metal line; and filling the trench with a metal material.
7. The method of claim 6 , wherein the trench extending through the second dielectric layer and the second etch stop layer includes an upper portion having a first width and a lower portion having a second width, wherein the first width is greater than the second width.
8. The method of claim 1 , wherein the forming the first metal line of the MLI structure includes: performing a lithography and etching process to form a trench in the first dielectric layer that exposes the conductive feature; filling the trench with a metal material; planarizing the metal material and the first dielectric layer, such that a top surface of the metal material is substantially planar with the top surface of the first dielectric layer; and etching back the metal material, such that the top surface of the metal material is lower than the top surface of the first dielectric layer.
9. A method for forming a multi-layer interconnection (MLI) structure over a substrate, the method comprising: forming a first dielectric layer; forming a first metal feature in the first dielectric layer, wherein the first metal feature has a first portion and a second portion, wherein the second portion is disposed over the first portion and a width of the second portion is greater than a width of the first portion; forming an etch stop layer on the first dielectric layer; forming a second dielectric layer on the etch stop layer, such that the etch stop layer is disposed between the first dielectric layer and the second dielectric layer; and forming a second metal feature in the second dielectric layer, wherein the second metal feature has a third portion and a fourth portion, wherein the fourth portion is disposed over the third portion and a width of the fourth portion is greater than a width of the third portion, and further wherein: the third portion of the second metal feature physically contacts the second portion of the first metal feature, and the third portion of the second metal feature includes a first sidewall and a second sidewall, wherein the first dielectric layer, the etch stop layer, and the second dielectric layer directly contact the first sidewall and the etch stop layer and the second dielectric layer directly contact the second sidewall.
10. The method of claim 9 , wherein the forming the first metal feature and the forming the second metal feature each include performing a dual damascene process.
11. The method of claim 9 , wherein the forming the second metal feature includes: etching a trench in the second dielectric layer that extends below a top surface of the first dielectric layer; lining the trench with a metal barrier layer; and filling the trench with a metal bulk layer, wherein the metal bulk layer is disposed over the metal barrier layer.
12. The method of claim 9 , wherein the forming the first metal feature includes etching back the first metal feature, such that a top surface of the first metal feature is lower than the top surface of the first dielectric layer and the etch stop layer includes a portion that extends below the top surface of the first dielectric layer.
13. The method of claim 9 , wherein the forming the first metal feature includes partially filling a trench with a metal material, such that a top surface of the first metal feature is lower than the top surface of the first dielectric layer and the etch stop layer includes a portion that extends below the top surface of the first dielectric layer.
14. The method of claim 9 , wherein the forming the first metal feature includes selectively growing a dielectric material over the first dielectric layer, thereby increasing a thickness of the first dielectric layer, such that a top surface of the first metal feature is lower than the top surface of the first dielectric layer and the etch stop layer includes a portion that extends below the top surface of the first dielectric layer.
15. The method of claim 9 , wherein the first metal feature has a thickness (T), and a ratio of a distance between a top surface of the first metal feature and a top surface of the first dielectric layer to the thickness is about 20% to about 30%.
16. A method for forming an interconnect structure, the method comprising: forming a first dielectric layer over a substrate; forming a metal line in the first dielectric layer, wherein a top surface of the metal line is below a top surface of the first dielectric layer, wherein the metal line is connected to an integrated circuit device feature; forming an etch stop layer on the top surface of the first dielectric layer and a portion of the top surface of the metal line; forming a second dielectric layer over the top surface of the first dielectric layer, wherein the etch stop layer is disposed between the first dielectric layer and the second dielectric layer; and forming a metal via in the second dielectric layer, wherein the metal via extends through the etch stop layer to physically contact the metal line, wherein the metal via has a first sidewall and a second sidewall, wherein the second dielectric layer and the etch stop layer directly contact the first sidewall and the second sidewall, and further wherein a portion of the first sidewall directly contacted by the etch stop layer is less than a portion of the second sidewall directly contacted by the etch stop layer.
17. The method of claim 16 , wherein the forming the metal line includes partially filling a trench in the first dielectric layer with a metal material, such that the top surface of the metal line is below the top surface of the first dielectric layer.
18. The method of claim 16 , wherein the forming the metal line includes selectively growing a dielectric material over the first dielectric layer, thereby increasing a thickness of the first dielectric layer, such that the top surface of the metal line is below the top surface of the first dielectric layer.
19. The method of claim 16 , wherein the forming the metal via includes: performing a first lithography process to form a first patterned mask layer over the second dielectric layer, wherein the first patterned mask layer has a first opening; performing a second lithography process to form a second patterned mask layer over the first patterned mask layer, wherein the second patterned mask layer has a second opening that overlaps the first opening and the second patterned mask layer partially fills the first opening; etching the second dielectric layer using the second patterned mask layer to form a trench that extends partially through the second dielectric layer; after removing the second patterned mask layer, etching the second dielectric layer using the first patterned mask layer, such that the trench extends through the second dielectric layer and the etch stop layer to expose the metal line; and filling the trench with a metal material.
20. The method of claim 19 , wherein the metal line is a first metal line and the forming the metal via also forms a second metal line, wherein the metal via connects the first metal line to the second metal line.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
May 10, 2019
April 21, 2020
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