A memory-testing method is adapted in a memory circuit including a first block and a second block including a plurality of row addresses and column addresses. The memory-testing method includes: selecting one of the row addresses and one of the column addresses as a testing row and a testing column according to selection logic; selecting sampled column addresses of the testing row and sampled row addresses of the testing column according to a sampling process; executing the read operation on the sampled column addresses of the testing row and the sampled row addresses of the testing column in the first block; determining whether the read fail rate of the first block exceeds a predetermined ratio; and marking the first block as an input/output fail when the read fail rate exceeds the predetermined ratio.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A memory-testing method adapted to a memory circuit, wherein the memory circuit includes a first block and a second block, wherein the first block and the second block comprise a plurality of row addresses and a plurality of column addresses, wherein the memory-testing method comprises: selecting one of the row addresses as a tested row according to selection logic; selecting one of the column addresses as a tested column according to the selection logic; selecting a plurality of sampled column addresses on the tested row according to a sampling procedure; selecting a plurality of sampled row addresses on the tested column according to the sampling procedure; executing a read operation on the sampled column addresses on the tested row of the first block; executing the read operation on the sampled row addresses on the tested column of the first block; determining whether a read fail rate of the read operations executed on the sampled column addresses on the tested row and the sampled row addresses on the tested column of the first block exceeds a predetermined ratio; and when the read fail rate exceeds the predetermined ratio, marking the first block as an input/output fail.
2. The memory-testing method of claim 1 , further comprising: when the read fail rate does not exceed the predetermined ratio or after the step of marking the first block as an input/output fail, executing the read operation on the sampled column addresses on the tested row of the second block; executing the read operation on the sampled row addresses on the tested column of the second block; determining whether the read fail rate of the read operations executed on the sampled column addresses on the tested row and the sampled row addresses on the tested column of the second block exceeds the predetermined ratio; and when the read fail rate exceeds the predetermined ratio, marking the second block as an input/output fail.
3. The memory-testing method of claim 2 , wherein when the first block and/or the second block are marked as an input/output fail, this indicates that peripheral circuits of the first block and/or the second block have malfunctioned and that the read fail rate is very high.
4. The memory-testing method of claim 1 , wherein the sampling procedure comprises: dividing the column addresses into a first number of column sections; selecting at least one of the column sections to be a selected column section, wherein the column sections other than the selected column section is an unselected column section; selecting the addresses of the selected column section to be the sampled column addresses; dividing the row addresses into a second number of row sections; selecting at least one of the row sections to be a selected row section, wherein the row sections other than the selected row section is an unselected row section; and selecting the addresses of the selected row section to be the sampled row addresses.
5. The memory-testing method of claim 4 , wherein the first number is equal to the second number.
6. The memory-testing method of claim 4 , wherein the step of selecting at least one of the column sections to be the selected column section further comprises: selecting half of the first number of column sections, wherein the selected column section is interlaced with the unselected column section.
7. The memory-testing method of claim 4 , wherein the step of selecting at least one of the row sections to be the selected row section further comprises: selecting half of the second number of row sections, wherein the selected row section is interlaced with the unselected row section.
8. The memory-testing method of claim 1 , wherein the step of determining whether the read fail rate of the read operation executed on the first block exceeds a predetermined ratio further comprises: determining whether the read fail rate of the first block is 100%; when the read fail rate is 100%, marking the first block as a solid input/output fail; and when the read fail rate is not 100%, marking the first block as a soft input/output fail.
9. A memory-testing method adapted in a memory circuit, wherein the memory circuit comprises a first block and a second block, wherein the first block and the second block comprise a plurality of row addresses and a plurality of column addresses, wherein the memory-testing method comprises: selecting one of the row addresses to be a tested row according to selection logic; selecting one of the column addresses as a tested column according to the selection logic; selecting a plurality of sampled column addresses on the tested row according to a sampling procedure; selecting a plurality of sampled row addresses on the tested column according to the sampling procedure; simultaneously executing a read operation on the sampled column addresses on the tested row of the first block and the second block; simultaneously executing the read operation on the sampled row addresses on the tested column of the first block and the second block; determining whether a read fail rate of the read operations executed on the sampled column addresses on the tested row and the sampled row addresses on the tested column of the memory circuit is 0; when the read fail ratio of the memory circuit is not 0 , determining whether the read fail ratio of the first block and/or the second block exceeds a predetermined ratio; and when the read fail ratio of the first block and/or the second block exceeds the predetermined ratio, marking the first block and/or the second block as a solid input/output fail.
10. The memory-testing method of claim 9 , wherein when the first block and/or the second block are marked as an input/output fail, this indicates that peripheral circuits of the first block and/or the second block have malfunctioned and that the read fail rate is very high.
11. The memory-testing method of claim 9 , wherein the sampling procedure comprises: dividing the column addresses into a first number of column sections; selecting at least one of the column sections to be a selected column section, wherein the column sections other than the selected column section is an unselected column section; selecting the addresses of the selected column section to be the sampled column addresses; dividing the row addresses into a second number of row sections; selecting at least one of the row sections to be a selected row section, wherein the row sections other than the selected row section is an unselected row section; and selecting the addresses of the selected row section to be the sampled row addresses.
12. The memory-testing method of claim 11 , wherein the first number is equal to the second number.
13. The memory-testing method of claim 11 , wherein the step of selecting at least one of the column sections to be the selected column section further comprises: selecting half of the first number of column sections, wherein the selected column section is interlaced with the unselected column section.
14. The memory-testing method of claim 11 , wherein the step of selecting at least one of the row sections to be the selected row section further comprises: selecting half of the second number of row sections, wherein the selected row section is interlaced with the unselected row section.
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June 8, 2018
April 28, 2020
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