Processing circuitry

1. A processing circuit comprising: a first time-encoding modulator configured to receive a first combined signal corresponding to a sum of a first input signal and a second input signal and to generate a first pulse-width-modulation (PWM) signal with a cycle frequency that depends substantially on the square of the value of the first combined signal; a second time-encoding modulator configured to receive a second combined signal corresponding to a difference between said first input signal and said second input signal and to generate a second PWM signal with a cycle frequency that depends substantially on the square of the value of the second combined signal; a first time-decoding converter configured to receive the first PWM signal and to provide a first count value based on a first parameter of the first PWM signal; a second time-decoding converter configured to receive the second PWM signal and to provide a second count value based on a second parameter of the second PWM signal; and a subtractor configured to determine a difference between the first and second count values and to output an output signal based on said difference between the first and second count values; wherein the first time-decoding converter and the second time-decoding converter each comprise a counter configured to receive a reference clock signal and count a number of PWM cycles in each of a succession of count periods defined by the reference clock signal to provide the respective first or second count value.

2. A processing circuit according to claim 1 , wherein the first parameter is a PWM cycle frequency of the first PWM signal and the second parameter is a PWM cycle frequency of the second PWM signal.

3. A processing circuit according to claim 1 , wherein the first parameter is a PWM cycle period of the first PWM signal and the second parameter is a PWM cycle period of the second PWM signal.

4. A processing circuit according to claim 1 wherein the first and second time-decoding converters each comprise a respective counter configured to receive a reference clock signal and wherein the processing circuit is selectively operable in a first mode or a second mode, wherein: in the first mode of operation the first and second parameters are PWM cycle frequencies of the first and second PWM signals respectively, and the counters of the first and second time-decoding converters are each configured count a number of PWM cycles in each of a succession of count periods defined by the reference clock signal to provide the count value; in the second mode of operation the first and second parameters are PWM cycle periods of the first and second PWM signals respectively, and the counters of the first and second time-decoding converters are each configured count a number of cycles of the reference clock signal in a PWM cycle period defined by the respective one of the first or second PWM signals to provide the count value; and the frequency of the reference clock signal is greater in the second mode than in the first mode.

5. A processing circuit according to claim 1 further comprising a signal combiner having a first combiner element configured to additively combine the first input signal and the second input signal to generate the first combined signal and a second combiner element configured to subtractively combine the first input signal and the second input signal to generate the second combined signal.

6. A processing circuit according to claim 5 wherein: the first combiner element comprises first and second current sources configured to provide currents defined by the first and second input signals respectively, wherein the first and second current sources are configured to supply current of the same polarity as one another to an output node of the first combiner element; and the second combiner element comprises third and fourth current sources configured to provide currents defined by the first and second input signals respectively, wherein the third and fourth current sources are configured to supply current of the opposite polarity as one another to an output node of the second combiner element.

7. A processing circuit according to claim 1 implemented as an integrated circuit.

8. An electronic device comprising a processing circuit according to claim 1 .

9. An electronic device as claimed in claim 8 wherein the device is at least one of: a battery powered device; a portable device; a communications device; a mobile telephone; a smartphone; a computing device; a laptop; notebook or tablet computer; a gaming device; a personal media player; a wearable device; a voice controlled device.

10. A processing circuit comprising: a first time-encoding modulator configured to receive a first combined signal corresponding to a sum of a first input signal and a second input signal and to generate a first pulse-width-modulation (PWM) signal with a cycle frequency that depends substantially on the square of the value of the first combined signal; a second time-encoding modulator configured to receive a second combined signal corresponding to a difference between said first input signal and said second input signal and to generate a second PWM signal with a cycle frequency that depends substantially on the square of the value of the second combined signal; a first time-decoding converter configured to receive the first PWM signal and to provide a first count value based on a first parameter of the first PWM signal; a second time-decoding converter configured to receive the second PWM signal and to provide a second count value based on a second parameter of the second PWM signal; and a subtractor configured to determine a difference between the first and second count values and to output an output signal based on said difference between the first and second count values; wherein the first time-decoding converter and the second time-decoding converter each comprise a counter configured to receive a reference clock signal and to count a number of cycles of the reference clock signal in a PWM cycle period defined by the respective one of the first or second PWM signals to provide the respective first or second count value.

11. A processing circuit according to claim 10 wherein the processing circuit is configured such the value of each of the first and second combined signals is limited to be no greater than a defined limit, such that a maximum variation in cycle frequency of the respective first or second PWM signals is no greater than 25%.

12. A processing circuit comprising: a first time-encoding modulator configured to receive a first combined signal corresponding to a sum of a first input signal and a second input signal and to generate a first pulse-width-modulation (PWM) signal with a cycle frequency that depends substantially on the square of the value of the first combined signal; a second time-encoding modulator configured to receive a second combined signal corresponding to a difference between said first input signal and said second input signal and to generate a second PWM signal with a cycle frequency that depends substantially on the square of the value of the second combined signal; a first time-decoding converter configured to receive the first PWM signal and to provide a first count value based on a first parameter of the first PWM signal; a second time-decoding converter configured to receive the second PWM signal and to provide a second count value based on a second parameter of the second PWM signal; and a subtractor configured to determine a difference between the first and second count values and to output an output signal based on said difference between the first and second count values; wherein each of the first time-encoding modulator and the second time-encoding modulator comprises: a forward signal path configured to receive the respective first or second combined signal at a first input; a feedback path forming a feedback loop with at least part of the forward signal path; a comparator located in the forward signal path within the feedback loop; and a filter arrangement within the feedback loop.

13. A processing circuit according to claim 12 wherein the comparator is a hysteretic comparator.

14. A processing circuit according to claim 12 , wherein the filter arrangement comprises a resistive-capacitive filter.

15. A processing circuit according to claim 12 , wherein each of the first time-encoding modulator and the second time-encoding modulator comprises: a current generator configured to receive the respective one of the first or second PWM signals output from the comparator and to generate a first controlled current signal having a first defined current during periods of a first voltage state of the PWM signal and a second controlled current signal during periods of a second voltage state of the PWM signal; and a capacitor configured to be charged and discharged by the first controlled current signal.

16. A multiplication circuit for multiplying a first input value by a second input value comprising: a first signal path configured to receive a first signal with a value corresponding to the sum of the first input value and the second input value and to generate a first output value which is a function of the square of the value of the first signal; a second signal path configured to receive a second signal with a value corresponding to the difference between the first input value and the second input value and to generate a second output value which is a function of the square of the value of the second signal; and a subtractor for determining a difference between the first output value and the second output value; wherein each of the first and second signal paths comprises a self-oscillating time-encoding modulator and a time-decoding converter; and wherein the time-decoding converter in each of the first and second signal paths comprises a respective counter configured to receive a reference clock signal and wherein the multiplication circuit is selectively operable in a first mode or a second mode, wherein: in the first mode of operation the counter of the time-decoding converter is configured count a number of cycles in an output of the respective self-oscillating time-encoding modulator in each of a succession of count periods defined by the reference clock signal to provide a count value; in the second mode of operation the counter of the time-decoding converter is configured to count a number of cycles of the reference clock signal in a cycle period defined by the output of the respective self-oscillating time-encoding modulator to provide the count value; and the frequency of the reference clock signal is greater in the second mode than in the first mode.

17. A multiplication circuit as claimed in claim 16 comprising a signal combiner configured to receive the first and second input values and generate the first and second signals.

18. A processing circuit comprising: a signal combiner configured to receive first and second input signals and to generate a first combined signal corresponding to a sum of the first and second input signals and a second combined signal corresponding to a difference between the first and second input signals; first and second time-encoding modulators configured to receive the first and second combined signals respectively and generate respective first and second cyclic signals each with a respective cycle frequency, wherein the respective cycle frequency is substantially proportional to (1−R 2 ) where R is a value of the respective input to the respective time-encoding modulator normalised within a range of −1 to +1 with respect to an input range of the respective time-encoding modulator; and first and second counters configured to receive the first and second cyclic signals respectively and produce first and second count values; and a subtractor configured to determine a difference between the first and second count values; wherein the first and second counters are each configured to generate a count value of a number of cycles of the first or the second cyclic signal in a count period defined by a reference clock signal.